An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy

Joohwan Lee, Kihyun Park, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A novel built-in redundancy analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing content addressable memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using linear feedback shift register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.

Original languageEnglish
Title of host publication2009 International SoC Design Conference, ISOCC 2009
Pages353-356
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
Duration: 2009 Nov 222009 Nov 24

Publication series

Name2009 International SoC Design Conference, ISOCC 2009

Other

Other2009 International SoC Design Conference, ISOCC 2009
CountryKorea, Republic of
CityBusan
Period09/11/2209/11/24

Fingerprint

Redundancy
Repair
Data storage equipment
Associative storage
Shift registers
Feedback

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Lee, J., Park, K., & Kang, S. (2009). An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy. In 2009 International SoC Design Conference, ISOCC 2009 (pp. 353-356). [5423846] (2009 International SoC Design Conference, ISOCC 2009). https://doi.org/10.1109/SOCDC.2009.5423846
Lee, Joohwan ; Park, Kihyun ; Kang, Sungho. / An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy. 2009 International SoC Design Conference, ISOCC 2009. 2009. pp. 353-356 (2009 International SoC Design Conference, ISOCC 2009).
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Lee, J, Park, K & Kang, S 2009, An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy. in 2009 International SoC Design Conference, ISOCC 2009., 5423846, 2009 International SoC Design Conference, ISOCC 2009, pp. 353-356, 2009 International SoC Design Conference, ISOCC 2009, Busan, Korea, Republic of, 09/11/22. https://doi.org/10.1109/SOCDC.2009.5423846

An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy. / Lee, Joohwan; Park, Kihyun; Kang, Sungho.

2009 International SoC Design Conference, ISOCC 2009. 2009. p. 353-356 5423846 (2009 International SoC Design Conference, ISOCC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lee J, Park K, Kang S. An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy. In 2009 International SoC Design Conference, ISOCC 2009. 2009. p. 353-356. 5423846. (2009 International SoC Design Conference, ISOCC 2009). https://doi.org/10.1109/SOCDC.2009.5423846