Abstract
A novel built-in redundancy analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing content addressable memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using linear feedback shift register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.
Original language | English |
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Title of host publication | 2009 International SoC Design Conference, ISOCC 2009 |
Pages | 353-356 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2009 Dec 1 |
Event | 2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of Duration: 2009 Nov 22 → 2009 Nov 24 |
Publication series
Name | 2009 International SoC Design Conference, ISOCC 2009 |
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Other
Other | 2009 International SoC Design Conference, ISOCC 2009 |
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Country | Korea, Republic of |
City | Busan |
Period | 09/11/22 → 09/11/24 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy. / Lee, Joohwan; Park, Kihyun; Kang, Sungho.
2009 International SoC Design Conference, ISOCC 2009. 2009. p. 353-356 5423846 (2009 International SoC Design Conference, ISOCC 2009).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy
AU - Lee, Joohwan
AU - Park, Kihyun
AU - Kang, Sungho
PY - 2009/12/1
Y1 - 2009/12/1
N2 - A novel built-in redundancy analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing content addressable memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using linear feedback shift register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.
AB - A novel built-in redundancy analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing content addressable memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using linear feedback shift register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.
UR - http://www.scopus.com/inward/record.url?scp=77951435886&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77951435886&partnerID=8YFLogxK
U2 - 10.1109/SOCDC.2009.5423846
DO - 10.1109/SOCDC.2009.5423846
M3 - Conference contribution
AN - SCOPUS:77951435886
SN - 9781424450343
T3 - 2009 International SoC Design Conference, ISOCC 2009
SP - 353
EP - 356
BT - 2009 International SoC Design Conference, ISOCC 2009
ER -