An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy

Joohwan Lee; Kihyun Park; Sungho Kang

doi:10.1109/SOCDC.2009.5423846

An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy

Joohwan Lee, Kihyun Park, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A novel built-in redundancy analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing content addressable memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using linear feedback shift register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.

Original language	English
Title of host publication	2009 International SoC Design Conference, ISOCC 2009
Pages	353-356
Number of pages	4
DOIs	https://doi.org/10.1109/SOCDC.2009.5423846
Publication status	Published - 2009
Event	2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of Duration: 2009 Nov 22 → 2009 Nov 24

Publication series

Name	2009 International SoC Design Conference, ISOCC 2009

Other

Other	2009 International SoC Design Conference, ISOCC 2009
Country	Korea, Republic of
City	Busan
Period	09/11/22 → 09/11/24

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/SOCDC.2009.5423846

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Cite this

@inproceedings{24f8aadf4a494ce994810cd0f33a0d20,

title = "An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy",

abstract = "A novel built-in redundancy analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing content addressable memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using linear feedback shift register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.",

author = "Joohwan Lee and Kihyun Park and Sungho Kang",

year = "2009",

doi = "10.1109/SOCDC.2009.5423846",

language = "English",

isbn = "9781424450343",

series = "2009 International SoC Design Conference, ISOCC 2009",

pages = "353--356",

booktitle = "2009 International SoC Design Conference, ISOCC 2009",

}

Lee, J, Park, K & Kang, S 2009, An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy. in 2009 International SoC Design Conference, ISOCC 2009., 5423846, 2009 International SoC Design Conference, ISOCC 2009, pp. 353-356, 2009 International SoC Design Conference, ISOCC 2009, Busan, Korea, Republic of, 09/11/22. https://doi.org/10.1109/SOCDC.2009.5423846

An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy. / Lee, Joohwan; Park, Kihyun; Kang, Sungho.

2009 International SoC Design Conference, ISOCC 2009. 2009. p. 353-356 5423846 (2009 International SoC Design Conference, ISOCC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy

AU - Lee, Joohwan

AU - Park, Kihyun

AU - Kang, Sungho

PY - 2009

Y1 - 2009

N2 - A novel built-in redundancy analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing content addressable memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using linear feedback shift register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.

AB - A novel built-in redundancy analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing content addressable memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using linear feedback shift register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.

UR - http://www.scopus.com/inward/record.url?scp=77951435886&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77951435886&partnerID=8YFLogxK

U2 - 10.1109/SOCDC.2009.5423846

DO - 10.1109/SOCDC.2009.5423846

M3 - Conference contribution

AN - SCOPUS:77951435886

SN - 9781424450343

T3 - 2009 International SoC Design Conference, ISOCC 2009

SP - 353

EP - 356

BT - 2009 International SoC Design Conference, ISOCC 2009

T2 - 2009 International SoC Design Conference, ISOCC 2009

Y2 - 22 November 2009 through 24 November 2009

ER -