An effective interfacing adapter for PRAM based main memory via flexible management DRAM buffer

Mei Ying Bian, Su Kyung Yoon, Shin-Dug Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An interfacing adapter is required between cache layer and PRAM based main memory to cover the shortcomings of PRAM. Thus this research is to design a flexible DRAM buffer (FDB) structure, which can improves performance by prefetch candidate data into FDB to reduce the miss penalty, and extends PRAM lifetime by filtering a large portion of write back data upon eviction from last level cache. Our results show that FDB can effectively minimize the access latency to achieve similar performance to the case of DRAM main memory and reduce a certain degree of write count to PRAM, thus limited endurance can get some respite thereby, typically extend their life expectancy.

Original languageEnglish
Title of host publicationIT Convergence and Security 2012
Pages1237-1242
Number of pages6
DOIs
Publication statusPublished - 2013 Feb 26
EventInternational Conference on IT Convergence and Security, ICITCS 2012 - Pyeong Chang, Korea, Republic of
Duration: 2012 Dec 52012 Dec 7

Publication series

NameLecture Notes in Electrical Engineering
Volume215 LNEE
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

Other

OtherInternational Conference on IT Convergence and Security, ICITCS 2012
CountryKorea, Republic of
CityPyeong Chang
Period12/12/512/12/7

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering

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  • Cite this

    Bian, M. Y., Yoon, S. K., & Kim, S-D. (2013). An effective interfacing adapter for PRAM based main memory via flexible management DRAM buffer. In IT Convergence and Security 2012 (pp. 1237-1242). (Lecture Notes in Electrical Engineering; Vol. 215 LNEE). https://doi.org/10.1007/978-94-007-5860-5_148