An effective parallel alpg using instruction for high speed memory testing

Hyunjun Yoon, Myung Hoon Yang, Yongjoon Kim, Youngkyu Park, Jaeseok Park, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents the design and implementation of a new parallel Algorithmic Pattern Generator (ALPG) of Automatic Test Equipment (ATE) for the high speed memory testing. We implemented the Instruction Analyzer (IA) that unrolls the instructions using simple instructions. And, unrolled instruction memory is also implemented to reduce the delay of the IA. These implementations allow the ALPG to operate flexible algorithms at high speed. For high speed, we also designed the ALPG of multiple Pattern Generators (PG) with phase-shifting clocks. Therefore, the ALPG has expandability and operates at high speed with the high flexibility of the algorithms.

Original languageEnglish
Title of host publication2008 International SoC Design Conference, ISOCC 2008
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
Duration: 2008 Nov 242008 Nov 25

Publication series

Name2008 International SoC Design Conference, ISOCC 2008
Volume1

Other

Other2008 International SoC Design Conference, ISOCC 2008
CountryKorea, Republic of
CityBusan
Period08/11/2408/11/25

Fingerprint

Data storage equipment
Testing
Clocks

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

Cite this

Yoon, H., Yang, M. H., Kim, Y., Park, Y., Park, J., & Kang, S. (2008). An effective parallel alpg using instruction for high speed memory testing. In 2008 International SoC Design Conference, ISOCC 2008 [4815649] (2008 International SoC Design Conference, ISOCC 2008; Vol. 1). https://doi.org/10.1109/SOCDC.2008.4815649
Yoon, Hyunjun ; Yang, Myung Hoon ; Kim, Yongjoon ; Park, Youngkyu ; Park, Jaeseok ; Kang, Sungho. / An effective parallel alpg using instruction for high speed memory testing. 2008 International SoC Design Conference, ISOCC 2008. 2008. (2008 International SoC Design Conference, ISOCC 2008).
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abstract = "This paper presents the design and implementation of a new parallel Algorithmic Pattern Generator (ALPG) of Automatic Test Equipment (ATE) for the high speed memory testing. We implemented the Instruction Analyzer (IA) that unrolls the instructions using simple instructions. And, unrolled instruction memory is also implemented to reduce the delay of the IA. These implementations allow the ALPG to operate flexible algorithms at high speed. For high speed, we also designed the ALPG of multiple Pattern Generators (PG) with phase-shifting clocks. Therefore, the ALPG has expandability and operates at high speed with the high flexibility of the algorithms.",
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Yoon, H, Yang, MH, Kim, Y, Park, Y, Park, J & Kang, S 2008, An effective parallel alpg using instruction for high speed memory testing. in 2008 International SoC Design Conference, ISOCC 2008., 4815649, 2008 International SoC Design Conference, ISOCC 2008, vol. 1, 2008 International SoC Design Conference, ISOCC 2008, Busan, Korea, Republic of, 08/11/24. https://doi.org/10.1109/SOCDC.2008.4815649

An effective parallel alpg using instruction for high speed memory testing. / Yoon, Hyunjun; Yang, Myung Hoon; Kim, Yongjoon; Park, Youngkyu; Park, Jaeseok; Kang, Sungho.

2008 International SoC Design Conference, ISOCC 2008. 2008. 4815649 (2008 International SoC Design Conference, ISOCC 2008; Vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Yoon H, Yang MH, Kim Y, Park Y, Park J, Kang S. An effective parallel alpg using instruction for high speed memory testing. In 2008 International SoC Design Conference, ISOCC 2008. 2008. 4815649. (2008 International SoC Design Conference, ISOCC 2008). https://doi.org/10.1109/SOCDC.2008.4815649