An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors

Woo Chan Park, Kil Whan Lee, Il San Kim, Tack Don Han, Sung Bong Yang

Research output: Contribution to journalArticlepeer-review

19 Citations (Scopus)


As a 3D scene becomes increasingly complex and the screen resolution increases, the design of an effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture that performs the depth test twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste due to fetching unnecessary obscured texture data by performing the depth test before texture mapping. It also reduces the miss penalties of the pixel cache by using a prefetch scheme - that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. We have built a trace-driven simulator for the proposed architecture. To validate the proposed architecture, the results of various simulations are provided. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption while producing high-performance gains.

Original languageEnglish
Pages (from-to)1501-1508
Number of pages8
JournalIEEE Transactions on Computers
Issue number11
Publication statusPublished - 2003 Nov

Bibliographical note

Funding Information:
The authors are grateful to the anonymous reviewers of the earlier version of this paper, whose incisive comments helped improve the presentation. This work is supported by the NRL-Fund from the Ministry of Science & Technology of Korea.

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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