An effective power reduction methodology for deterministic BIST using auxiliary LFSR

Myung Hoon Yang, Yongjoon Kim, Sunghoon Chun, Sungho Kang

Research output: Contribution to journalArticle

3 Citations (Scopus)


Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.

Original languageEnglish
Pages (from-to)591-595
Number of pages5
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Issue number6
Publication statusPublished - 2008 Dec 1


All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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