An effective power reduction methodology for deterministic BIST using auxiliary LFSR

Myung Hoon Yang, Yongjoon Kim, Sunghoon Chun, Sungho Kang

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.

Original languageEnglish
Pages (from-to)591-595
Number of pages5
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume24
Issue number6
DOIs
Publication statusPublished - 2008 Dec 1

Fingerprint

Built-in self test
Testing
Electric power utilization
Detectors
Hardware

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{f0340dc9816d49d4bb4b2f6c2f696fee,
title = "An effective power reduction methodology for deterministic BIST using auxiliary LFSR",
abstract = "Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.",
author = "Yang, {Myung Hoon} and Yongjoon Kim and Sunghoon Chun and Sungho Kang",
year = "2008",
month = "12",
day = "1",
doi = "10.1007/s10836-008-5077-z",
language = "English",
volume = "24",
pages = "591--595",
journal = "Journal of Electronic Testing: Theory and Applications (JETTA)",
issn = "0923-8174",
publisher = "Springer Netherlands",
number = "6",

}

An effective power reduction methodology for deterministic BIST using auxiliary LFSR. / Yang, Myung Hoon; Kim, Yongjoon; Chun, Sunghoon; Kang, Sungho.

In: Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 24, No. 6, 01.12.2008, p. 591-595.

Research output: Contribution to journalArticle

TY - JOUR

T1 - An effective power reduction methodology for deterministic BIST using auxiliary LFSR

AU - Yang, Myung Hoon

AU - Kim, Yongjoon

AU - Chun, Sunghoon

AU - Kang, Sungho

PY - 2008/12/1

Y1 - 2008/12/1

N2 - Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.

AB - Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.

UR - http://www.scopus.com/inward/record.url?scp=57249095850&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=57249095850&partnerID=8YFLogxK

U2 - 10.1007/s10836-008-5077-z

DO - 10.1007/s10836-008-5077-z

M3 - Article

AN - SCOPUS:57249095850

VL - 24

SP - 591

EP - 595

JO - Journal of Electronic Testing: Theory and Applications (JETTA)

JF - Journal of Electronic Testing: Theory and Applications (JETTA)

SN - 0923-8174

IS - 6

ER -