An effective rasterization architecture for mobile vector graphics processors

Jinhong Park, Jinwoo Kim, Woo Chan Park, Youngsik Kim, Chelho Jeong, Tack-Don Han

Research output: Contribution to journalArticle

Abstract

This paper proposed a novel index board rasterization architecture which reduces mathematical calculations and memory traffic for vector graphics. The proposed architecture uses the cell based method which has advantages in computational complexity, and generates the active span by referring to only valid cells and placing them in scanline order with two internal SRAMs. The proposed architecture reduces the amount of calculation by an average of 59.4% and also the external memory traffic by an average of 30.0% compared to the traditional architecture.

Original languageEnglish
Pages (from-to)835-841
Number of pages7
JournalIEICE Electronics Express
Volume8
Issue number11
DOIs
Publication statusPublished - 2011 Jun 20

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central processing units
Data storage equipment
Static random access storage
traffic
Computational complexity
cells
Rasterization

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Park, Jinhong ; Kim, Jinwoo ; Park, Woo Chan ; Kim, Youngsik ; Jeong, Chelho ; Han, Tack-Don. / An effective rasterization architecture for mobile vector graphics processors. In: IEICE Electronics Express. 2011 ; Vol. 8, No. 11. pp. 835-841.
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An effective rasterization architecture for mobile vector graphics processors. / Park, Jinhong; Kim, Jinwoo; Park, Woo Chan; Kim, Youngsik; Jeong, Chelho; Han, Tack-Don.

In: IEICE Electronics Express, Vol. 8, No. 11, 20.06.2011, p. 835-841.

Research output: Contribution to journalArticle

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