Abstract
As more cores are integrated in a single chip with sophisticated process like nano technology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 15th Asian Test Symposium 2006 |
| Pages | 279-284 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2006 Dec 1 |
| Event | 15th Asian Test Symposium 2006 - Fukuoka, Japan Duration: 2006 Nov 20 → 2006 Nov 23 |
Publication series
| Name | Proceedings of the Asian Test Symposium |
|---|---|
| Volume | 2006 |
| ISSN (Print) | 1081-7735 |
Other
| Other | 15th Asian Test Symposium 2006 |
|---|---|
| Country | Japan |
| City | Fukuoka |
| Period | 06/11/20 → 06/11/23 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Cite this
Kim, Y., Yang, M. H., Park, Y., Lee, D. Y., & Kang, S. (2006). An effective test pattern generation for testing signal integrity. In Proceedings of the 15th Asian Test Symposium 2006 (pp. 279-284). [4030780] (Proceedings of the Asian Test Symposium; Vol. 2006). https://doi.org/10.1109/ATS.2006.261032