Abstract
As more cores are integrated in a single chip with sophisticated process like nano technology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 15th Asian Test Symposium 2006 |
| Pages | 279-284 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2006 Dec 1 |
| Event | 15th Asian Test Symposium 2006 - Fukuoka, Japan Duration: 2006 Nov 20 → 2006 Nov 23 |
Publication series
| Name | Proceedings of the Asian Test Symposium |
|---|---|
| Volume | 2006 |
| ISSN (Print) | 1081-7735 |
Other
| Other | 15th Asian Test Symposium 2006 |
|---|---|
| Country | Japan |
| City | Fukuoka |
| Period | 06/11/20 → 06/11/23 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
}
An effective test pattern generation for testing signal integrity. / Kim, Yongjoon; Yang, Myung Hoon; Park, Youngkyu; Lee, Dae Yeal; Kang, Sungho.
Proceedings of the 15th Asian Test Symposium 2006. 2006. p. 279-284 4030780 (Proceedings of the Asian Test Symposium; Vol. 2006).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - An effective test pattern generation for testing signal integrity
AU - Kim, Yongjoon
AU - Yang, Myung Hoon
AU - Park, Youngkyu
AU - Lee, Dae Yeal
AU - Kang, Sungho
PY - 2006/12/1
Y1 - 2006/12/1
N2 - As more cores are integrated in a single chip with sophisticated process like nano technology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme.
AB - As more cores are integrated in a single chip with sophisticated process like nano technology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme.
UR - http://www.scopus.com/inward/record.url?scp=33947634054&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33947634054&partnerID=8YFLogxK
U2 - 10.1109/ATS.2006.261032
DO - 10.1109/ATS.2006.261032
M3 - Conference contribution
SN - 0769526284
SN - 9780769526287
T3 - Proceedings of the Asian Test Symposium
SP - 279
EP - 284
BT - Proceedings of the 15th Asian Test Symposium 2006
ER -