As more cores are integrated in a single chip with sophisticated process like nano technology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme.
|Title of host publication||Proceedings of the 15th Asian Test Symposium 2006|
|Number of pages||6|
|Publication status||Published - 2006|
|Event||15th Asian Test Symposium 2006 - Fukuoka, Japan|
Duration: 2006 Nov 20 → 2006 Nov 23
|Name||Proceedings of the Asian Test Symposium|
|Other||15th Asian Test Symposium 2006|
|Period||06/11/20 → 06/11/23|
Bibliographical noteFunding Information:
This research was supported in part by a research grant from Southern Illinois University at Edwardsville. I thank graduate students, HyungJun Cho, Ming Zhou, and Murali Neralla, for their assistance in coding the analytical method and simulation and running the experiments. I also thank the department editor and anonymous referees for their useful comments.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering