Analog and mixed-signal testing is becomming an important issue that affects both the time-to-market and product cost of many SoCs. In order to provide an efficient test method for the PLL which is a mixed-signal circuit widely used in most of SoCs, a novel BIST method is developed. It uses the change of phase differences generated by selectively alternating the feedback frequency. This BIST can be easily implemented with several counters and combinational logic gates. The simulation results show higher fault coverage than that of previous test methods. Thus it provides an efficient structural test, which is suitable for a production test in terms of an area overhead, a test accessibility, and test time.