An efficient built-in self-repair scheme for area reduction

Keewon Cho, Young Woo Lee, Sungyoul Seo, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As memory densities have drastically increased, memory faults have become the major factor of the decline in the yield. One powerful solution is built-in redundancy analysis (BIRA) which repairs faulty cells with spare lines. However, area overhead of BIRA should be carefully considered because a chip area is limited. In order to maximize the yield and minimize area overhead simultaneously, this paper proposes an efficient built-in self-repair (BISR) scheme. The proposed scheme performs the memory test process twice, so that faulty addresses can be stored efficiently. Experimental results show that the proposed BIRA can obtain optimal repair rate with very small area overhead.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages105-106
Number of pages2
ISBN (Electronic)9781538622858
DOIs
Publication statusPublished - 2018 May 29
Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
Duration: 2017 Nov 52017 Nov 8

Publication series

NameProceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other14th International SoC Design Conference, ISOCC 2017
CountryKorea, Republic of
CitySeoul
Period17/11/517/11/8

Fingerprint

Redundancy
Repair
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Cho, K., Lee, Y. W., Seo, S., & Kang, S. (2018). An efficient built-in self-repair scheme for area reduction. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 105-106). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368791
Cho, Keewon ; Lee, Young Woo ; Seo, Sungyoul ; Kang, Sungho. / An efficient built-in self-repair scheme for area reduction. Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 105-106 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).
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Cho, K, Lee, YW, Seo, S & Kang, S 2018, An efficient built-in self-repair scheme for area reduction. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 105-106, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368791

An efficient built-in self-repair scheme for area reduction. / Cho, Keewon; Lee, Young Woo; Seo, Sungyoul; Kang, Sungho.

Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 105-106 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Cho K, Lee YW, Seo S, Kang S. An efficient built-in self-repair scheme for area reduction. In Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 105-106. (Proceedings - International SoC Design Conference 2017, ISOCC 2017). https://doi.org/10.1109/ISOCC.2017.8368791