An efficient built-in self-repair scheme for area reduction

Keewon Cho; Young Woo Lee; Sungyoul Seo; Sungho Kang

doi:10.1109/ISOCC.2017.8368791

An efficient built-in self-repair scheme for area reduction

Keewon Cho, Young Woo Lee, Sungyoul Seo, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

As memory densities have drastically increased, memory faults have become the major factor of the decline in the yield. One powerful solution is built-in redundancy analysis (BIRA) which repairs faulty cells with spare lines. However, area overhead of BIRA should be carefully considered because a chip area is limited. In order to maximize the yield and minimize area overhead simultaneously, this paper proposes an efficient built-in self-repair (BISR) scheme. The proposed scheme performs the memory test process twice, so that faulty addresses can be stored efficiently. Experimental results show that the proposed BIRA can obtain optimal repair rate with very small area overhead.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	105-106
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368791
Publication status	Published - 2018 May 29
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2017.8368791

Cite this

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title = "An efficient built-in self-repair scheme for area reduction",

abstract = "As memory densities have drastically increased, memory faults have become the major factor of the decline in the yield. One powerful solution is built-in redundancy analysis (BIRA) which repairs faulty cells with spare lines. However, area overhead of BIRA should be carefully considered because a chip area is limited. In order to maximize the yield and minimize area overhead simultaneously, this paper proposes an efficient built-in self-repair (BISR) scheme. The proposed scheme performs the memory test process twice, so that faulty addresses can be stored efficiently. Experimental results show that the proposed BIRA can obtain optimal repair rate with very small area overhead.",

author = "Keewon Cho and Lee, {Young Woo} and Sungyoul Seo and Sungho Kang",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 14th International SoC Design Conference, ISOCC 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

year = "2018",

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doi = "10.1109/ISOCC.2017.8368791",

language = "English",

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Cho, K, Lee, YW, Seo, S & Kang, S 2018, An efficient built-in self-repair scheme for area reduction. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 105-106, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368791

An efficient built-in self-repair scheme for area reduction. / Cho, Keewon; Lee, Young Woo; Seo, Sungyoul et al.

Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 105-106 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - An efficient built-in self-repair scheme for area reduction

AU - Cho, Keewon

AU - Lee, Young Woo

AU - Seo, Sungyoul

AU - Kang, Sungho

PY - 2018/5/29

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N2 - As memory densities have drastically increased, memory faults have become the major factor of the decline in the yield. One powerful solution is built-in redundancy analysis (BIRA) which repairs faulty cells with spare lines. However, area overhead of BIRA should be carefully considered because a chip area is limited. In order to maximize the yield and minimize area overhead simultaneously, this paper proposes an efficient built-in self-repair (BISR) scheme. The proposed scheme performs the memory test process twice, so that faulty addresses can be stored efficiently. Experimental results show that the proposed BIRA can obtain optimal repair rate with very small area overhead.

AB - As memory densities have drastically increased, memory faults have become the major factor of the decline in the yield. One powerful solution is built-in redundancy analysis (BIRA) which repairs faulty cells with spare lines. However, area overhead of BIRA should be carefully considered because a chip area is limited. In order to maximize the yield and minimize area overhead simultaneously, this paper proposes an efficient built-in self-repair (BISR) scheme. The proposed scheme performs the memory test process twice, so that faulty addresses can be stored efficiently. Experimental results show that the proposed BIRA can obtain optimal repair rate with very small area overhead.

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BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 14th International SoC Design Conference, ISOCC 2017

Y2 - 5 November 2017 through 8 November 2017

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An efficient built-in self-repair scheme for area reduction

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