Abstract
We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.
| Original language | English |
|---|---|
| Title of host publication | 2003 IEEE Workshop on Signal Processing Systems |
| Subtitle of host publication | Design and Implementation, SIPS 2003 |
| Editors | Wonyong Sung, Myung Hoon Sunwoo |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 41-44 |
| Number of pages | 4 |
| ISBN (Electronic) | 0780377958 |
| DOIs | |
| Publication status | Published - 2003 Jan 1 |
| Event | 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 - Seoul, Korea, Republic of Duration: 2003 Aug 27 → 2003 Aug 29 |
Publication series
| Name | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
|---|---|
| Volume | 2003-January |
| ISSN (Print) | 1520-6130 |
Other
| Other | 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 |
|---|---|
| Country | Korea, Republic of |
| City | Seoul |
| Period | 03/8/27 → 03/8/29 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Signal Processing
- Applied Mathematics
- Hardware and Architecture
Cite this
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An efficient high-speed block turbo code decoding algorithm and hardware architecture design. / Yoo, Kyungchul; Shin, Hyungshik; Jung, Yunho; Lee, Junghyuck; Kim, Jaeseok.
2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003. ed. / Wonyong Sung; Myung Hoon Sunwoo. Institute of Electrical and Electronics Engineers Inc., 2003. p. 41-44 1235641 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2003-January).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - An efficient high-speed block turbo code decoding algorithm and hardware architecture design
AU - Yoo, Kyungchul
AU - Shin, Hyungshik
AU - Jung, Yunho
AU - Lee, Junghyuck
AU - Kim, Jaeseok
PY - 2003/1/1
Y1 - 2003/1/1
N2 - We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.
AB - We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.
UR - http://www.scopus.com/inward/record.url?scp=84943265571&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84943265571&partnerID=8YFLogxK
U2 - 10.1109/SIPS.2003.1235641
DO - 10.1109/SIPS.2003.1235641
M3 - Conference contribution
AN - SCOPUS:84943265571
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 41
EP - 44
BT - 2003 IEEE Workshop on Signal Processing Systems
A2 - Sung, Wonyong
A2 - Sunwoo, Myung Hoon
PB - Institute of Electrical and Electronics Engineers Inc.
ER -