Abstract
We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.
Original language | English |
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Title of host publication | 2003 IEEE Workshop on Signal Processing Systems |
Subtitle of host publication | Design and Implementation, SIPS 2003 |
Editors | Wonyong Sung, Myung Hoon Sunwoo |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 41-44 |
Number of pages | 4 |
ISBN (Electronic) | 0780377958 |
DOIs | |
Publication status | Published - 2003 |
Event | 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 - Seoul, Korea, Republic of Duration: 2003 Aug 27 → 2003 Aug 29 |
Publication series
Name | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
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Volume | 2003-January |
ISSN (Print) | 1520-6130 |
Other
Other | 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 |
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Country/Territory | Korea, Republic of |
City | Seoul |
Period | 03/8/27 → 03/8/29 |
Bibliographical note
Publisher Copyright:© 2003 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Signal Processing
- Applied Mathematics
- Hardware and Architecture