An efficient high-speed block turbo code decoding algorithm and hardware architecture design

Kyungchul Yoo, Hyungshik Shin, Yunho Jung, Junghyuck Lee, Jaeseok Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.

Original languageEnglish
Title of host publication2003 IEEE Workshop on Signal Processing Systems
Subtitle of host publicationDesign and Implementation, SIPS 2003
EditorsWonyong Sung, Myung Hoon Sunwoo
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages41-44
Number of pages4
ISBN (Electronic)0780377958
DOIs
Publication statusPublished - 2003 Jan 1
Event2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 - Seoul, Korea, Republic of
Duration: 2003 Aug 272003 Aug 29

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Volume2003-January
ISSN (Print)1520-6130

Other

Other2003 IEEE Workshop on Signal Processing Systems, SIPS 2003
CountryKorea, Republic of
CitySeoul
Period03/8/2703/8/29

Fingerprint

Turbo Codes
Turbo codes
Hardware Architecture
Block Codes
Decoding
High Speed
Hardware
Iterative Decoding
Iterative decoding
Log-likelihood Ratio
Logic Synthesis
Logic gates
Gaussian distribution
Standard deviation
High Performance
Logic
Data storage equipment
Design

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

Cite this

Yoo, K., Shin, H., Jung, Y., Lee, J., & Kim, J. (2003). An efficient high-speed block turbo code decoding algorithm and hardware architecture design. In W. Sung, & M. H. Sunwoo (Eds.), 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003 (pp. 41-44). [1235641] (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIPS.2003.1235641
Yoo, Kyungchul ; Shin, Hyungshik ; Jung, Yunho ; Lee, Junghyuck ; Kim, Jaeseok. / An efficient high-speed block turbo code decoding algorithm and hardware architecture design. 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003. editor / Wonyong Sung ; Myung Hoon Sunwoo. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 41-44 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).
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Yoo, K, Shin, H, Jung, Y, Lee, J & Kim, J 2003, An efficient high-speed block turbo code decoding algorithm and hardware architecture design. in W Sung & MH Sunwoo (eds), 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003., 1235641, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 41-44, 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003, Seoul, Korea, Republic of, 03/8/27. https://doi.org/10.1109/SIPS.2003.1235641

An efficient high-speed block turbo code decoding algorithm and hardware architecture design. / Yoo, Kyungchul; Shin, Hyungshik; Jung, Yunho; Lee, Junghyuck; Kim, Jaeseok.

2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003. ed. / Wonyong Sung; Myung Hoon Sunwoo. Institute of Electrical and Electronics Engineers Inc., 2003. p. 41-44 1235641 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Yoo K, Shin H, Jung Y, Lee J, Kim J. An efficient high-speed block turbo code decoding algorithm and hardware architecture design. In Sung W, Sunwoo MH, editors, 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 41-44. 1235641. (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). https://doi.org/10.1109/SIPS.2003.1235641