An efficient high-speed block turbo code decoding algorithm and hardware architecture design

Kyungchul Yoo; Hyungshik Shin; Yunho Jung; Junghyuck Lee; Jaeseok Kim

doi:10.1109/SIPS.2003.1235641

An efficient high-speed block turbo code decoding algorithm and hardware architecture design

Kyungchul Yoo, Hyungshik Shin, Yunho Jung, Junghyuck Lee, Jaeseok Kim

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.

Original language	English
Title of host publication	2003 IEEE Workshop on Signal Processing Systems
Subtitle of host publication	Design and Implementation, SIPS 2003
Editors	Wonyong Sung, Myung Hoon Sunwoo
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	41-44
Number of pages	4
ISBN (Electronic)	0780377958
DOIs	https://doi.org/10.1109/SIPS.2003.1235641
Publication status	Published - 2003
Event	2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 - Seoul, Korea, Republic of Duration: 2003 Aug 27 → 2003 Aug 29

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Volume	2003-January
ISSN (Print)	1520-6130

Other

Other	2003 IEEE Workshop on Signal Processing Systems, SIPS 2003
Country/Territory	Korea, Republic of
City	Seoul
Period	03/8/27 → 03/8/29

Bibliographical note

Publisher Copyright:
© 2003 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Signal Processing
Applied Mathematics
Hardware and Architecture

Access to Document

10.1109/SIPS.2003.1235641

Cite this

Yoo, K., Shin, H., Jung, Y., Lee, J., & Kim, J. (2003). An efficient high-speed block turbo code decoding algorithm and hardware architecture design. In W. Sung, & M. H. Sunwoo (Eds.), 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003 (pp. 41-44). [1235641] (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIPS.2003.1235641

Yoo, Kyungchul ; Shin, Hyungshik ; Jung, Yunho ; Lee, Junghyuck ; Kim, Jaeseok. / An efficient high-speed block turbo code decoding algorithm and hardware architecture design. 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003. editor / Wonyong Sung ; Myung Hoon Sunwoo. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 41-44 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).

@inproceedings{aaffc2a66a3d463ca277deb2f2df8e90,

title = "An efficient high-speed block turbo code decoding algorithm and hardware architecture design",

abstract = "We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.",

author = "Kyungchul Yoo and Hyungshik Shin and Yunho Jung and Junghyuck Lee and Jaeseok Kim",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 ; Conference date: 27-08-2003 Through 29-08-2003",

year = "2003",

doi = "10.1109/SIPS.2003.1235641",

language = "English",

series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "41--44",

editor = "Wonyong Sung and Sunwoo, {Myung Hoon}",

booktitle = "2003 IEEE Workshop on Signal Processing Systems",

address = "United States",

}

Yoo, K, Shin, H, Jung, Y, Lee, J & Kim, J 2003, An efficient high-speed block turbo code decoding algorithm and hardware architecture design. in W Sung & MH Sunwoo (eds), 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003., 1235641, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 41-44, 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003, Seoul, Korea, Republic of, 03/8/27. https://doi.org/10.1109/SIPS.2003.1235641

An efficient high-speed block turbo code decoding algorithm and hardware architecture design. / Yoo, Kyungchul; Shin, Hyungshik; Jung, Yunho; Lee, Junghyuck; Kim, Jaeseok.

2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003. ed. / Wonyong Sung; Myung Hoon Sunwoo. Institute of Electrical and Electronics Engineers Inc., 2003. p. 41-44 1235641 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - An efficient high-speed block turbo code decoding algorithm and hardware architecture design

AU - Yoo, Kyungchul

AU - Shin, Hyungshik

AU - Jung, Yunho

AU - Lee, Junghyuck

AU - Kim, Jaeseok

PY - 2003

Y1 - 2003

N2 - We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.

AB - We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.

UR - http://www.scopus.com/inward/record.url?scp=84943265571&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84943265571&partnerID=8YFLogxK

U2 - 10.1109/SIPS.2003.1235641

DO - 10.1109/SIPS.2003.1235641

M3 - Conference contribution

AN - SCOPUS:84943265571

T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

SP - 41

EP - 44

BT - 2003 IEEE Workshop on Signal Processing Systems

A2 - Sung, Wonyong

A2 - Sunwoo, Myung Hoon

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003

Y2 - 27 August 2003 through 29 August 2003

ER -

Yoo K, Shin H, Jung Y, Lee J, Kim J. An efficient high-speed block turbo code decoding algorithm and hardware architecture design. In Sung W, Sunwoo MH, editors, 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation, SIPS 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 41-44. 1235641. (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). https://doi.org/10.1109/SIPS.2003.1235641

An efficient high-speed block turbo code decoding algorithm and hardware architecture design

Abstract

Publication series

Other

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this