An efficient pipelined parallel architecture for blocking effect removal in hdtv

This paper presents an efficient architecture for blocking effect removal in HDTV. Since there is a lot of image signal for signal processing in digital HDTV, the memory size and the fast operation have been the main concerns of the DSP(Digital Signal Processing) architectures. To reduce the size of a memory, a memory is partitioned into many memory banks. This makes it possible to access the memory concurrently. Also, to improve the operation speed, a pipelined parallel architecture and a memory scheduling technique are adopted. Since multiplications and divisions are time-critical, these operations are replaced with shifiings. Therefore this architecture is very fast and uses small size memory banks, and this makes it possible to realize a real-time signal processor.