An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC

Yong Lee, Sungyoul Seo, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the existing DFT(Design for Test) circuitry. The experimental results show that the proposed method can drastically reduce test cost, ATE dependence and testing complexity.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages176-179
Number of pages4
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

Fingerprint

Data compression
Clocks
Controllers
Testing
Costs

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lee, Y., Seo, S., & Kang, S. (2013). An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 176-179). [6863965] IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6863965
Lee, Yong ; Seo, Sungyoul ; Kang, Sungho. / An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC. ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. pp. 176-179
@inproceedings{de7b3afaefb8479ca6f99d7f66e3bcfa,
title = "An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC",
abstract = "RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the existing DFT(Design for Test) circuitry. The experimental results show that the proposed method can drastically reduce test cost, ATE dependence and testing complexity.",
author = "Yong Lee and Sungyoul Seo and Sungho Kang",
year = "2013",
month = "1",
day = "1",
doi = "10.1109/ISOCC.2013.6863965",
language = "English",
isbn = "9781479911417",
pages = "176--179",
booktitle = "ISOCC 2013 - 2013 International SoC Design Conference",
publisher = "IEEE Computer Society",
address = "United States",

}

Lee, Y, Seo, S & Kang, S 2013, An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC. in ISOCC 2013 - 2013 International SoC Design Conference., 6863965, IEEE Computer Society, pp. 176-179, 2013 International SoC Design Conference, ISOCC 2013, Busan, Korea, Republic of, 13/11/17. https://doi.org/10.1109/ISOCC.2013.6863965

An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC. / Lee, Yong; Seo, Sungyoul; Kang, Sungho.

ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. p. 176-179 6863965.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC

AU - Lee, Yong

AU - Seo, Sungyoul

AU - Kang, Sungho

PY - 2013/1/1

Y1 - 2013/1/1

N2 - RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the existing DFT(Design for Test) circuitry. The experimental results show that the proposed method can drastically reduce test cost, ATE dependence and testing complexity.

AB - RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the existing DFT(Design for Test) circuitry. The experimental results show that the proposed method can drastically reduce test cost, ATE dependence and testing complexity.

UR - http://www.scopus.com/inward/record.url?scp=84906918573&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84906918573&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2013.6863965

DO - 10.1109/ISOCC.2013.6863965

M3 - Conference contribution

AN - SCOPUS:84906918573

SN - 9781479911417

SP - 176

EP - 179

BT - ISOCC 2013 - 2013 International SoC Design Conference

PB - IEEE Computer Society

ER -

Lee Y, Seo S, Kang S. An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC. In ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society. 2013. p. 176-179. 6863965 https://doi.org/10.1109/ISOCC.2013.6863965