An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC

Yong Lee, Sungyoul Seo, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the existing DFT(Design for Test) circuitry. The experimental results show that the proposed method can drastically reduce test cost, ATE dependence and testing complexity.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages176-179
Number of pages4
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Publication series

NameISOCC 2013 - 2013 International SoC Design Conference

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC'. Together they form a unique fingerprint.

Cite this