Scan-based test and diagnosis are important for improving yield of nanometer-scale chips. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method is proposed for not only stuck-at fault but also transition fault. The proposed method is implemented simply and provides maximum diagnosis resolution for stuck-at and transition faults.
|Title of host publication||Proceedings - 2019 International SoC Design Conference, ISOCC 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2019 Oct|
|Event||16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of|
Duration: 2019 Oct 6 → 2019 Oct 9
|Name||Proceedings - 2019 International SoC Design Conference, ISOCC 2019|
|Conference||16th International System-on-Chip Design Conference, ISOCC 2019|
|Country/Territory||Korea, Republic of|
|Period||19/10/6 → 19/10/9|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by Samsung Electronics Company, Ltd., Hwasung, Korea.
© 2019 IEEE.
All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering
- Artificial Intelligence
- Hardware and Architecture