Exploiting internal parallelism over hundreds NAND flash memory is becoming a key design issue in high-speed Solid State Disks (SSDs). In this work, we simulated a cycle-accurate SSD platform with twenty four page allocation strategies, geared toward exploiting both system-level parallelism and flash-level parallelism with a variety of design parameters. Our extensive experimental analysis reveals that 1) the previously-proposed channel-and-way striping based page allocation scheme is not the best from a performance perspective, 2) As opposed to the current perception that system and flash-level concurrency mechanisms are largely orthogonal, flash-level parallelism are interfered by the system-level concurrency mechanism employed, and 3) With most of the current parallel data access methods, internal resources are significantly underutilized. Finally, we present several optimization points to achieve maximum internal parallelism.
|Publication status||Published - 2012|
|Event||4th USENIX Workshop on Hot Topics in Storage and File Systems, HotStorage 2012 - Boston, United States|
Duration: 2012 Jun 13 → 2012 Jun 14
|Conference||4th USENIX Workshop on Hot Topics in Storage and File Systems, HotStorage 2012|
|Period||12/6/13 → 12/6/14|
Bibliographical noteFunding Information:
We thank our shepherd, Umesh Maheshwari, for his help and careful revisions in improving our paper. We also thank anonymous reviewers for their constructive feedback. This work is supported in part by NSF grants 1017882, 0937949, and 0833126 and DOE grant DESC0002156.
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Hardware and Architecture
- Information Systems