TY - GEN
T1 - An experimental study on the package stress in plastic encapsulated IC (integrated circuit)
AU - Lee, Minju
AU - Joo, Won Gu
PY - 2001/1/1
Y1 - 2001/1/1
N2 - Transfer molding is the primary process for IC (integrated circuit) encapsulation with EMC (epoxy molding compound) and also the most extensive method for plastic packaging. Plastic encapsulated packages offer many advantages over their other counterparts such as low cost, light weight, and ready availability that accounted for approximately 98% of IC packages produced within the microelectronics industry. The recent trends in plastic packaging are packages becoming thinner and smaller where drawbacks are more serious in terms of package stress from the transfer molding process. It is for this reason that the need for thorough understanding of package stress is becoming greater. In this paper, flow-induced package stress is experimentally visualized to analyze time-dependence flow characteristics of EMC by employing different geometrical gate design parameters. Also, EMCs with different material properties are evaluated to quantify their influence on package stress in terms of interfacial adhesion, warpage, voiding, wire sweep, and penetration rate. In addition, screening DOE (design of experiments) is performed to identify the main process parameters, and the optimum window of critical parameters is defined by RSM (response surface methodology).
AB - Transfer molding is the primary process for IC (integrated circuit) encapsulation with EMC (epoxy molding compound) and also the most extensive method for plastic packaging. Plastic encapsulated packages offer many advantages over their other counterparts such as low cost, light weight, and ready availability that accounted for approximately 98% of IC packages produced within the microelectronics industry. The recent trends in plastic packaging are packages becoming thinner and smaller where drawbacks are more serious in terms of package stress from the transfer molding process. It is for this reason that the need for thorough understanding of package stress is becoming greater. In this paper, flow-induced package stress is experimentally visualized to analyze time-dependence flow characteristics of EMC by employing different geometrical gate design parameters. Also, EMCs with different material properties are evaluated to quantify their influence on package stress in terms of interfacial adhesion, warpage, voiding, wire sweep, and penetration rate. In addition, screening DOE (design of experiments) is performed to identify the main process parameters, and the optimum window of critical parameters is defined by RSM (response surface methodology).
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U2 - 10.1109/EMAP.2001.983996
DO - 10.1109/EMAP.2001.983996
M3 - Conference contribution
AN - SCOPUS:84925985580
T3 - Advances in Electronic Materials and Packaging 2001
SP - 268
EP - 273
BT - Advances in Electronic Materials and Packaging 2001
A2 - Lee, S.B.
A2 - Paik, K.W.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd International Symposium on Electronic Materials and Packaging, EMAP 2001
Y2 - 19 November 2001 through 22 November 2001
ER -