An FPGA implementation of whitted-style ray tracing accelerator

Woo Chan Park; Jae Ho Nah; Jeong Soo Park; Kyung Ho Lee; Dong Seok Kim; Sang Duk Kim; Jin Hong Park; Cheong Ghil Kim; Yoon Sig Kang; Sung Bong Yang; Tack Don Han

doi:10.1109/RT.2008.4634650

An FPGA implementation of whitted-style ray tracing accelerator

Woo Chan Park, Jae Ho Nah, Jeong Soo Park, Kyung Ho Lee, Dong Seok Kim, Sang Duk Kim, Jin Hong Park, Cheong Ghil Kim, Yoon Sig Kang, Sung Bong Yang, Tack Don Han

College of Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3M rays per second over realistic 3D scenes. The future implementation with ASIC is expected to achieve real-time performance.

Original language	English
Title of host publication	RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings
Pages	187
Number of pages	1
DOIs	https://doi.org/10.1109/RT.2008.4634650
Publication status	Published - 2008
Event	RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008 - Los Angeles, CA, United States Duration: 2008 Aug 9 → 2008 Aug 10

Publication series

Name	RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings

Other

Other	RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008
Country/Territory	United States
City	Los Angeles, CA
Period	08/8/9 → 08/8/10

All Science Journal Classification (ASJC) codes

Computer Vision and Pattern Recognition
Electrical and Electronic Engineering

Access to Document

10.1109/RT.2008.4634650

Cite this

Park, W. C., Nah, J. H., Park, J. S., Lee, K. H., Kim, D. S., Kim, S. D., Park, J. H., Kim, C. G., Kang, Y. S., Yang, S. B., & Han, T. D. (2008). An FPGA implementation of whitted-style ray tracing accelerator. In RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings (pp. 187). [4634650] (RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings). https://doi.org/10.1109/RT.2008.4634650

@inproceedings{14d8306544854f6082fbbba81eac7b68,

title = "An FPGA implementation of whitted-style ray tracing accelerator",

abstract = "This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3M rays per second over realistic 3D scenes. The future implementation with ASIC is expected to achieve real-time performance.",

author = "Park, {Woo Chan} and Nah, {Jae Ho} and Park, {Jeong Soo} and Lee, {Kyung Ho} and Kim, {Dong Seok} and Kim, {Sang Duk} and Park, {Jin Hong} and Kim, {Cheong Ghil} and Kang, {Yoon Sig} and Yang, {Sung Bong} and Han, {Tack Don}",

year = "2008",

doi = "10.1109/RT.2008.4634650",

language = "English",

isbn = "9781424427413",

series = "RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings",

pages = "187",

booktitle = "RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings",

note = "RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008 ; Conference date: 09-08-2008 Through 10-08-2008",

}

Park, WC, Nah, JH, Park, JS, Lee, KH, Kim, DS, Kim, SD, Park, JH, Kim, CG, Kang, YS, Yang, SB & Han, TD 2008, An FPGA implementation of whitted-style ray tracing accelerator. in RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings., 4634650, RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings, pp. 187, RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Los Angeles, CA, United States, 08/8/9. https://doi.org/10.1109/RT.2008.4634650

An FPGA implementation of whitted-style ray tracing accelerator. / Park, Woo Chan; Nah, Jae Ho; Park, Jeong Soo et al.

RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings. 2008. p. 187 4634650 (RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Park, Woo Chan

AU - Nah, Jae Ho

AU - Park, Jeong Soo

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AU - Kim, Dong Seok

AU - Kim, Sang Duk

AU - Park, Jin Hong

AU - Kim, Cheong Ghil

AU - Kang, Yoon Sig

AU - Yang, Sung Bong

AU - Han, Tack Don

PY - 2008

Y1 - 2008

N2 - This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3M rays per second over realistic 3D scenes. The future implementation with ASIC is expected to achieve real-time performance.

AB - This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3M rays per second over realistic 3D scenes. The future implementation with ASIC is expected to achieve real-time performance.

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BT - RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings

T2 - RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008

Y2 - 9 August 2008 through 10 August 2008

ER -

An FPGA implementation of whitted-style ray tracing accelerator

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