An FPGA implementation of whitted-style ray tracing accelerator

Woo Chan Park, Jae Ho Nah, Jeong Soo Park, Kyung Ho Lee, Dong Seok Kim, Sang Duk Kim, Jin Hong Park, Cheong Ghil Kim, Yoon Sig Kang, Sung Bong Yang, Tack Don Han

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3M rays per second over realistic 3D scenes. The future implementation with ASIC is expected to achieve real-time performance.

Original languageEnglish
Title of host publicationRT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings
Number of pages1
DOIs
Publication statusPublished - 2008 Nov 28
EventRT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008 - Los Angeles, CA, United States
Duration: 2008 Aug 92008 Aug 10

Publication series

NameRT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings

Other

OtherRT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008
CountryUnited States
CityLos Angeles, CA
Period08/8/908/8/10

All Science Journal Classification (ASJC) codes

  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering

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  • Cite this

    Park, W. C., Nah, J. H., Park, J. S., Lee, K. H., Kim, D. S., Kim, S. D., Park, J. H., Kim, C. G., Kang, Y. S., Yang, S. B., & Han, T. D. (2008). An FPGA implementation of whitted-style ray tracing accelerator. In RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings [4634650] (RT'08 - IEEE/EG Symposium on Interactive Ray Tracing 2008, Proceedings). https://doi.org/10.1109/RT.2008.4634650