Non-Volatile Memory Express (NVMe) is designed with the goal of unlocking the potential of low-latency, randomaccess, memory-based storage devices. Specifically, NVMe employs various rich communication and queuing mechanism that can ideally schedule four billion I/O instructions for a single storage device. To explore NVMe with assorted user scenarios, we model diverse interface-level design parameters such as PCI Express, NVMe protocol, and different rich queuing mechanisms by considering a wide spectrum of host-level system configurations. In this work, we also assemble a comprehensive memory stack with different types of emerging NVM technologies, which can give us detailed NVMe related statistics like I/O request lifespans and I/O thread-related parallelism. Our evaluation results reveal that, i) while NVMe handshaking is light-weight for flash memory that uses block-based accesses (Block NVM), it can impose tremendous overheads for memristor technology (DRAM-like NVM), ii) in contrast to the common expectation, the performance of an NVMe-equipped system may not improve in a scalable fashion as the queue depth and the number of queues increase, and iii) more- and deeperqueue systems atop a Block NVM can significantly suffer from tremendous host-side memory requirements, whereas a DRAMlike NVM can cause frequent system stalls due to NVMe's inefficient interrupt service routine.
|Title of host publication||2016 5th Non-Volatile Memory Systems and Applications Symposium, NVMSA 2016|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2016 Aug 17|
|Event||5th Non-Volatile Memory Systems and Applications Symposium, NVMSA 2016 - Daegu, Korea, Republic of|
Duration: 2016 Aug 17 → 2016 Aug 19
|Name||2016 5th Non-Volatile Memory Systems and Applications Symposium, NVMSA 2016|
|Other||5th Non-Volatile Memory Systems and Applications Symposium, NVMSA 2016|
|Country||Korea, Republic of|
|Period||16/8/17 → 16/8/19|
Bibliographical noteFunding Information:
This research is supported in part by NRF grants 2016R1C1B2015312, 2015M3C4A7065645, and IITP grant, 2015-R0346-15-1008. This work is also supported in part by NSF grants 1213052, 1205618, 1302557, 1526750, 1409095, and 1439021. Mahmut Kandemir and Myoungsoo Jung are the co-corresponding authors.
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture