As the technology node of the dynamic random-access memory (DRAM) continues to decrease below the 10-nm-class, bit-cell failures due to the external environments have increased. As a result, DRAM vendors perform post package inspections to provide fault-free DRAMs to the end customers. However, post package inspections require considerable test costs. To overcome this issue, an in-DRAM built-in self-test (BIST) mechanism is implemented in this study as an alternative solution. Herein, we propose compact and high test-coverage features for the in-DRAM BIST that to resolve the area problem when applied to a commodity DRAM. The proposed BIST secures the same test coverage with a shorter time than the conventional BIST. The proposed BIST reduces the test time by 52% of the DDR BIST in functions with the same test coverages. Further, the implemented BIST can achieved an area overhead of 0.051% based on a 16Gb DDR4 DRAM in the second generation of the 10-nm-class DRAM process.
|Number of pages||11|
|Publication status||Published - 2021|
Bibliographical notePublisher Copyright:
© 2013 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Science(all)
- Materials Science(all)
- Electrical and Electronic Engineering