An in-order SMT architecture with static resource partitioning for consumer applications

Research output: Contribution to journalConference article

3 Citations (Scopus)

Abstract

This paper proposes a simplified simultaneous multithreading (SMT) architecture aiming at CPU cores of embedded SoCs for consumer applications. This architecture reduces the hardware cost and design complexity of the SMT architecture by adopting in-order execution within threads and static resource partitioning among threads. In our architecture, processor resources are divided into three types depending on their related pipeline stages and static partitioning is applied individually to each resource type. Each thread can perform its operation using the resource partition to which it belongs. Simulation results show that reasonable static partitioning reduces the hardware cost and design complexity of SMT processors while having little negative impact on or even improving performance, compared with full resource sharing.

Original languageEnglish
Pages (from-to)539-544
Number of pages6
JournalLecture Notes in Computer Science
Volume3320
DOIs
Publication statusPublished - 2004
Event5th International Conference, PDCAT 2004 - , Singapore
Duration: 2004 Dec 82004 Dec 10

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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