Abstract
Next generation non-volatile memory devices are promising replacements for DRAM and Flash memories for mobile devices because of their energy efficiency and non-volatile characteristics. In this paper, we propose a new memory hierarchy system for next-generation non-volatile memory devices that is called an integrated memory-disk (IM-D) structure. It can merge a conventional main memory layer and a disk storage layer into a single memory layer using Phase change memory (PCM) and Flash memories. The IM-D architecture, consisting of a dual buffering IM-D adapter to improve the limited endurance and latencies, an array of PCM/Flash hybrid memories, and an associated memory management module called the IM-D translation layer in the operating system, is designed to utilize the advantages of next-generation non-volatile memory devices and at the same time overcome some shortcomings, like the asymmetric read/write access latencies and limited endurance, of a conventional memory hierarchy system. In the IM-D architecture, we propose an array of PCM/Flash hybrid memories and a migration scheme to enhance the cost effective performance and to reduce access latency. Our experimental results show that the miss rate of the proposed IM-D adapter is reduced by 49 % as compared with the conventional memory module, and the write count is reduced by 60.15 %. In addition, the access latency of the IM-D storage is improved by 45.3 %.
| Original language | English |
|---|---|
| Pages (from-to) | 609-626 |
| Number of pages | 18 |
| Journal | Design Automation for Embedded Systems |
| Volume | 17 |
| Issue number | 3-4 |
| DOIs | |
| Publication status | Published - 2013 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
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An integrated memory-disk system with buffering adapter and non-volatile memory. / Yoon, Su Kyung; Bian, Mei Ying; Kim, Shin-Dug.
In: Design Automation for Embedded Systems, Vol. 17, No. 3-4, 01.01.2013, p. 609-626.Research output: Contribution to journal › Article
TY - JOUR
T1 - An integrated memory-disk system with buffering adapter and non-volatile memory
AU - Yoon, Su Kyung
AU - Bian, Mei Ying
AU - Kim, Shin-Dug
PY - 2013/1/1
Y1 - 2013/1/1
N2 - Next generation non-volatile memory devices are promising replacements for DRAM and Flash memories for mobile devices because of their energy efficiency and non-volatile characteristics. In this paper, we propose a new memory hierarchy system for next-generation non-volatile memory devices that is called an integrated memory-disk (IM-D) structure. It can merge a conventional main memory layer and a disk storage layer into a single memory layer using Phase change memory (PCM) and Flash memories. The IM-D architecture, consisting of a dual buffering IM-D adapter to improve the limited endurance and latencies, an array of PCM/Flash hybrid memories, and an associated memory management module called the IM-D translation layer in the operating system, is designed to utilize the advantages of next-generation non-volatile memory devices and at the same time overcome some shortcomings, like the asymmetric read/write access latencies and limited endurance, of a conventional memory hierarchy system. In the IM-D architecture, we propose an array of PCM/Flash hybrid memories and a migration scheme to enhance the cost effective performance and to reduce access latency. Our experimental results show that the miss rate of the proposed IM-D adapter is reduced by 49 % as compared with the conventional memory module, and the write count is reduced by 60.15 %. In addition, the access latency of the IM-D storage is improved by 45.3 %.
AB - Next generation non-volatile memory devices are promising replacements for DRAM and Flash memories for mobile devices because of their energy efficiency and non-volatile characteristics. In this paper, we propose a new memory hierarchy system for next-generation non-volatile memory devices that is called an integrated memory-disk (IM-D) structure. It can merge a conventional main memory layer and a disk storage layer into a single memory layer using Phase change memory (PCM) and Flash memories. The IM-D architecture, consisting of a dual buffering IM-D adapter to improve the limited endurance and latencies, an array of PCM/Flash hybrid memories, and an associated memory management module called the IM-D translation layer in the operating system, is designed to utilize the advantages of next-generation non-volatile memory devices and at the same time overcome some shortcomings, like the asymmetric read/write access latencies and limited endurance, of a conventional memory hierarchy system. In the IM-D architecture, we propose an array of PCM/Flash hybrid memories and a migration scheme to enhance the cost effective performance and to reduce access latency. Our experimental results show that the miss rate of the proposed IM-D adapter is reduced by 49 % as compared with the conventional memory module, and the write count is reduced by 60.15 %. In addition, the access latency of the IM-D storage is improved by 45.3 %.
UR - http://www.scopus.com/inward/record.url?scp=84908122763&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84908122763&partnerID=8YFLogxK
U2 - 10.1007/s10617-014-9152-7
DO - 10.1007/s10617-014-9152-7
M3 - Article
AN - SCOPUS:84908122763
VL - 17
SP - 609
EP - 626
JO - Design Automation for Embedded Systems
JF - Design Automation for Embedded Systems
SN - 0929-5585
IS - 3-4
ER -