An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM

Taehui Na, Jisu Kim, Byungkyu Song, Jung Pill Kim, Seung H. Kang, Seong Ook Jung

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual Vref sensing scheme (DVSS) that selectively uses an optimal Vref between Vref+ and Vref- is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal Vref is selected after fabrication, and the calibrated switch control bit, which contains Vref selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with 2× faster sensing speed and 1.5× lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

Original languageEnglish
Article number7194850
Pages (from-to)1361-1370
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number4
DOIs
Publication statusPublished - 2016 Apr 1

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Random access storage
Electric potential
Torque
Switches
Data storage equipment
Fabrication
Degradation
Industry
Monte Carlo simulation

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Na, Taehui ; Kim, Jisu ; Song, Byungkyu ; Kim, Jung Pill ; Kang, Seung H. ; Jung, Seong Ook. / An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016 ; Vol. 24, No. 4. pp. 1361-1370.
@article{230b5e02910b4029bba6f1033518b2da,
title = "An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM",
abstract = "Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual Vref sensing scheme (DVSS) that selectively uses an optimal Vref between Vref+ and Vref- is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal Vref is selected after fabrication, and the calibrated switch control bit, which contains Vref selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24{\%} for 32 Mb (6.1 sigma) with 2× faster sensing speed and 1.5× lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.",
author = "Taehui Na and Jisu Kim and Byungkyu Song and Kim, {Jung Pill} and Kang, {Seung H.} and Jung, {Seong Ook}",
year = "2016",
month = "4",
day = "1",
doi = "10.1109/TVLSI.2015.2453192",
language = "English",
volume = "24",
pages = "1361--1370",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM. / Na, Taehui; Kim, Jisu; Song, Byungkyu; Kim, Jung Pill; Kang, Seung H.; Jung, Seong Ook.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 4, 7194850, 01.04.2016, p. 1361-1370.

Research output: Contribution to journalArticle

TY - JOUR

T1 - An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM

AU - Na, Taehui

AU - Kim, Jisu

AU - Song, Byungkyu

AU - Kim, Jung Pill

AU - Kang, Seung H.

AU - Jung, Seong Ook

PY - 2016/4/1

Y1 - 2016/4/1

N2 - Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual Vref sensing scheme (DVSS) that selectively uses an optimal Vref between Vref+ and Vref- is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal Vref is selected after fabrication, and the calibrated switch control bit, which contains Vref selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with 2× faster sensing speed and 1.5× lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

AB - Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual Vref sensing scheme (DVSS) that selectively uses an optimal Vref between Vref+ and Vref- is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal Vref is selected after fabrication, and the calibrated switch control bit, which contains Vref selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with 2× faster sensing speed and 1.5× lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

UR - http://www.scopus.com/inward/record.url?scp=84939447965&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84939447965&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2015.2453192

DO - 10.1109/TVLSI.2015.2453192

M3 - Article

VL - 24

SP - 1361

EP - 1370

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 4

M1 - 7194850

ER -