An on-chip error detection method to reduce the post-silicon debug time

Hyunggoy Oh, Taewoo Han, Inhyuk Choi, Sungho Kang

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

Original languageEnglish
Article number7464321
Pages (from-to)38-44
Number of pages7
JournalIEEE Transactions on Computers
Volume66
Issue number1
DOIs
Publication statusPublished - 2017 Jan 1

Fingerprint

Error Detection
Error detection
Silicon
Chip
Buffer
Networks (circuits)
Trace
Compaction
Circuit Design
Internal
Interval
Experimental Results

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Software
  • Hardware and Architecture
  • Computational Theory and Mathematics

Cite this

Oh, Hyunggoy ; Han, Taewoo ; Choi, Inhyuk ; Kang, Sungho. / An on-chip error detection method to reduce the post-silicon debug time. In: IEEE Transactions on Computers. 2017 ; Vol. 66, No. 1. pp. 38-44.
@article{f331383157f94b7ebae3bed14f15ddb5,
title = "An on-chip error detection method to reduce the post-silicon debug time",
abstract = "Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.",
author = "Hyunggoy Oh and Taewoo Han and Inhyuk Choi and Sungho Kang",
year = "2017",
month = "1",
day = "1",
doi = "10.1109/TC.2016.2561920",
language = "English",
volume = "66",
pages = "38--44",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "1",

}

An on-chip error detection method to reduce the post-silicon debug time. / Oh, Hyunggoy; Han, Taewoo; Choi, Inhyuk; Kang, Sungho.

In: IEEE Transactions on Computers, Vol. 66, No. 1, 7464321, 01.01.2017, p. 38-44.

Research output: Contribution to journalArticle

TY - JOUR

T1 - An on-chip error detection method to reduce the post-silicon debug time

AU - Oh, Hyunggoy

AU - Han, Taewoo

AU - Choi, Inhyuk

AU - Kang, Sungho

PY - 2017/1/1

Y1 - 2017/1/1

N2 - Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

AB - Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

UR - http://www.scopus.com/inward/record.url?scp=85006988031&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85006988031&partnerID=8YFLogxK

U2 - 10.1109/TC.2016.2561920

DO - 10.1109/TC.2016.2561920

M3 - Article

AN - SCOPUS:85006988031

VL - 66

SP - 38

EP - 44

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 1

M1 - 7464321

ER -