Analysis and design of low-power continuous-time delta-sigma modulator using negative-R assisted integrator

Moonhyung Jang; Changuk Lee; Youngcheol Chae

doi:10.1109/JSSC.2018.2871111

Analysis and design of low-power continuous-time delta-sigma modulator using negative-R assisted integrator

Moonhyung Jang, Changuk Lee, Youngcheol Chae

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

23 Citations (Scopus)

Abstract

The opamp in the integrators of a continuous-time delta-sigma modulator (CTDSM) has stringent noise and linearity requirements, which lead to large power dissipation. In this paper, a negative-R assisted integrator is proposed to mitigate the opamp's requirements including dc gain, unity gain bandwidth, thermal and 1/f noise, and linearity, thus enabling a drastic power reduction. We present two prototype CTDSMs using the negative-R assisted integrators that employ a single-bit and tri-level feedback digital-to-analog converter (DAC), respectively. The prototype CTDSMs were fabricated in 65-nm CMOS technology. The first CTDSM using a single-bit feedback DAC achieves dynamic range (DR)/signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 93.1/88.5/100.5 dB in a 20-kHz bandwidth while dissipating only 55 μW from a 1.2-V supply. The second CTDSM, with a tri-level feedback DAC, achieves DR/SNDR/SFDR of 98.2/94.1/107 dB in a 24-kHz bandwidth while dissipating only 68 μW from a 1.2-V supply. The figures of merit of the two CTDSMs are 178.7 and 183.6 dB, respectively, which are the best energy efficiency among state-of-the-art works.

Original language	English
Article number	8486729
Pages (from-to)	277-287
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	54
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2018.2871111
Publication status	Published - 2019 Jan

Bibliographical note

Funding Information:
Manuscript received May 31, 2018; revised August 4, 2018 and September 13, 2018; accepted September 13, 2018. Date of publication October 9, 2018; date of current version January 14, 2019. This work was supported in part by the National Research Foundation of Korea through Korea Government under Grant MSIT 2018R1A4A1025986, in part by the Ministry of Trade, Industry, and Energy under Project 10080488, and in part by the Korea Semiconductor Research Consortium Support Program for the development of the future semiconductor device. This paper was approved by Associate Editor Jeffrey Gealow. (Corresponding author: Youngcheol Chae.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: ychae@yonsei.ac.kr).

Publisher Copyright:
© 1966-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/JSSC.2018.2871111

Cite this

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title = "Analysis and design of low-power continuous-time delta-sigma modulator using negative-R assisted integrator",

abstract = "The opamp in the integrators of a continuous-time delta-sigma modulator (CTDSM) has stringent noise and linearity requirements, which lead to large power dissipation. In this paper, a negative-R assisted integrator is proposed to mitigate the opamp's requirements including dc gain, unity gain bandwidth, thermal and 1/f noise, and linearity, thus enabling a drastic power reduction. We present two prototype CTDSMs using the negative-R assisted integrators that employ a single-bit and tri-level feedback digital-to-analog converter (DAC), respectively. The prototype CTDSMs were fabricated in 65-nm CMOS technology. The first CTDSM using a single-bit feedback DAC achieves dynamic range (DR)/signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 93.1/88.5/100.5 dB in a 20-kHz bandwidth while dissipating only 55 μW from a 1.2-V supply. The second CTDSM, with a tri-level feedback DAC, achieves DR/SNDR/SFDR of 98.2/94.1/107 dB in a 24-kHz bandwidth while dissipating only 68 μW from a 1.2-V supply. The figures of merit of the two CTDSMs are 178.7 and 183.6 dB, respectively, which are the best energy efficiency among state-of-the-art works.",

author = "Moonhyung Jang and Changuk Lee and Youngcheol Chae",

note = "Funding Information: Manuscript received May 31, 2018; revised August 4, 2018 and September 13, 2018; accepted September 13, 2018. Date of publication October 9, 2018; date of current version January 14, 2019. This work was supported in part by the National Research Foundation of Korea through Korea Government under Grant MSIT 2018R1A4A1025986, in part by the Ministry of Trade, Industry, and Energy under Project 10080488, and in part by the Korea Semiconductor Research Consortium Support Program for the development of the future semiconductor device. This paper was approved by Associate Editor Jeffrey Gealow. (Corresponding author: Youngcheol Chae.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: ychae@yonsei.ac.kr). Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

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Analysis and design of low-power continuous-time delta-sigma modulator using negative-R assisted integrator

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

UN SDGs

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