Analysis and design of low-power continuous-time delta-sigma modulator using negative-R assisted integrator

Moonhyung Jang, Changuk Lee, Youngcheol Chae

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

The opamp in the integrators of a continuous-time delta-sigma modulator (CTDSM) has stringent noise and linearity requirements, which lead to large power dissipation. In this paper, a negative-R assisted integrator is proposed to mitigate the opamp's requirements including dc gain, unity gain bandwidth, thermal and 1/f noise, and linearity, thus enabling a drastic power reduction. We present two prototype CTDSMs using the negative-R assisted integrators that employ a single-bit and tri-level feedback digital-to-analog converter (DAC), respectively. The prototype CTDSMs were fabricated in 65-nm CMOS technology. The first CTDSM using a single-bit feedback DAC achieves dynamic range (DR)/signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 93.1/88.5/100.5 dB in a 20-kHz bandwidth while dissipating only 55 μW from a 1.2-V supply. The second CTDSM, with a tri-level feedback DAC, achieves DR/SNDR/SFDR of 98.2/94.1/107 dB in a 24-kHz bandwidth while dissipating only 68 μW from a 1.2-V supply. The figures of merit of the two CTDSMs are 178.7 and 183.6 dB, respectively, which are the best energy efficiency among state-of-the-art works.

Original languageEnglish
Article number8486729
Pages (from-to)277-287
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number1
DOIs
Publication statusPublished - 2019 Jan

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this