Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique

Hyoseong Choi, Jiwon Lee, Jeonghoon Choi, Won Woo Ro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

AI and big data applications with large memory footprints are rapidly increasing. The memory footprint of applications may exceed the main memory, and accordingly, the need for high-speed processing of large data is increasing. This paper proposes a method to utilize a DRAM-based Network of DRAM (NoD) as a swap space. The Swap transfers data in units of 4KB pages, and conventionally, disks use 512 or 4096 bytes as a minimum data access unit. However, by utilizing DRAM's byte-addressability characteristic and latency hiding technique, necessary data can be read from the swap space in 64 bytes. For NoD architecture verification, a full system experiment environment is built using gem5 and DRAMsim3 simulators. For applications with frequent swap operations (XSBench, HPCG, and Ibm), the proposed technique achieves an average performance improvement of 12.3%.

Original languageEnglish
Title of host publicationITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages239-242
Number of pages4
ISBN (Electronic)9781665485593
DOIs
Publication statusPublished - 2022
Event37th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2022 - Phuket, Thailand
Duration: 2022 Jul 52022 Jul 8

Publication series

NameITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference37th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2022
Country/TerritoryThailand
CityPhuket
Period22/7/522/7/8

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. NRF-2021R1A2B5B01002932, Development of High Performance Multi-GPU Memory System, 50%) and Samsung Electronics Co., Ltd (IO201210-07936-01, 50%).

Publisher Copyright:
© 2022 IEEE.

All Science Journal Classification (ASJC) codes

  • Information Systems
  • Electrical and Electronic Engineering
  • Artificial Intelligence
  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture

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