Analysis of DRAM standby current failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor

M. H. Cho; Y. I. Kim; J. Choi; D. S. Woo; K. P. Lee; Y. J. Park; W. S. Lee; B. I. Ryu

Analysis of DRAM standby current failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor

M. H. Cho, Y. I. Kim, J. Choi, D. S. Woo, K. P. Lee, Y. J. Park, W. S. Lee, B. I. Ryu

Department of Physics

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify the mechanism of a standby current failure due to hot carrier degradation.

Original language	English
Pages	186-188
Number of pages	3
Publication status	Published - 2005
Event	ISTFA 2005 - 31st International Symposium for Testing and Failure Analysis - San Jose, CA, United States Duration: 2005 Nov 6 → 2005 Nov 10

Other

Other	ISTFA 2005 - 31st International Symposium for Testing and Failure Analysis
Country	United States
City	San Jose, CA
Period	05/11/6 → 05/11/10

All Science Journal Classification (ASJC) codes

Control and Systems Engineering
Safety, Risk, Reliability and Quality
Electrical and Electronic Engineering

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title = "Analysis of DRAM standby current failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor",

abstract = "A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify the mechanism of a standby current failure due to hot carrier degradation.",

author = "Cho, {M. H.} and Kim, {Y. I.} and J. Choi and Woo, {D. S.} and Lee, {K. P.} and Park, {Y. J.} and Lee, {W. S.} and Ryu, {B. I.}",

year = "2005",

language = "English",

pages = "186--188",

note = "ISTFA 2005 - 31st International Symposium for Testing and Failure Analysis ; Conference date: 06-11-2005 Through 10-11-2005",

}

Analysis of DRAM standby current failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor. / Cho, M. H.; Kim, Y. I.; Choi, J.; Woo, D. S.; Lee, K. P.; Park, Y. J.; Lee, W. S.; Ryu, B. I.

2005. 186-188 Paper presented at ISTFA 2005 - 31st International Symposium for Testing and Failure Analysis, San Jose, CA, United States.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Analysis of DRAM standby current failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor

AU - Cho, M. H.

AU - Kim, Y. I.

AU - Choi, J.

AU - Woo, D. S.

AU - Lee, K. P.

AU - Park, Y. J.

AU - Lee, W. S.

AU - Ryu, B. I.

PY - 2005

Y1 - 2005

N2 - A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify the mechanism of a standby current failure due to hot carrier degradation.

AB - A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify the mechanism of a standby current failure due to hot carrier degradation.

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M3 - Paper

AN - SCOPUS:33645670986

SP - 186

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T2 - ISTFA 2005 - 31st International Symposium for Testing and Failure Analysis

Y2 - 6 November 2005 through 10 November 2005

ER -

Analysis of DRAM standby current failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor

Abstract

Other

All Science Journal Classification (ASJC) codes

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