Analysis of DRAM standby current failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor

M. H. Cho, Y. I. Kim, J. Choi, D. S. Woo, K. P. Lee, Y. J. Park, W. S. Lee, B. I. Ryu

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify the mechanism of a standby current failure due to hot carrier degradation.

Original languageEnglish
Pages186-188
Number of pages3
Publication statusPublished - 2005 Dec 1
EventISTFA 2005 - 31st International Symposium for Testing and Failure Analysis - San Jose, CA, United States
Duration: 2005 Nov 62005 Nov 10

Other

OtherISTFA 2005 - 31st International Symposium for Testing and Failure Analysis
CountryUnited States
CitySan Jose, CA
Period05/11/605/11/10

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

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    Cho, M. H., Kim, Y. I., Choi, J., Woo, D. S., Lee, K. P., Park, Y. J., Lee, W. S., & Ryu, B. I. (2005). Analysis of DRAM standby current failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor. 186-188. Paper presented at ISTFA 2005 - 31st International Symposium for Testing and Failure Analysis, San Jose, CA, United States.