Abstract
Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.
| Original language | English |
|---|---|
| Title of host publication | PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 65-68 |
| Number of pages | 4 |
| ISBN (Print) | 9781538653869 |
| DOIs | |
| Publication status | Published - 2018 Aug 8 |
| Event | 14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018 - Prague, Czech Republic Duration: 2018 Jul 2 → 2018 Jul 5 |
Other
| Other | 14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018 |
|---|---|
| Country | Czech Republic |
| City | Prague |
| Period | 18/7/2 → 18/7/5 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
- Instrumentation
Cite this
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Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM. / Kim, Suk Min; Song, Byungkyu; Oh, Tae Woo; Jung, Seong Ook.
PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics. Institute of Electrical and Electronics Engineers Inc., 2018. p. 65-68 8430359.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM
AU - Kim, Suk Min
AU - Song, Byungkyu
AU - Oh, Tae Woo
AU - Jung, Seong Ook
PY - 2018/8/8
Y1 - 2018/8/8
N2 - Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.
AB - Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.
UR - http://www.scopus.com/inward/record.url?scp=85052495935&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85052495935&partnerID=8YFLogxK
U2 - 10.1109/PRIME.2018.8430359
DO - 10.1109/PRIME.2018.8430359
M3 - Conference contribution
SN - 9781538653869
SP - 65
EP - 68
BT - PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics
PB - Institute of Electrical and Electronics Engineers Inc.
ER -