Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.
|Title of host publication||PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2018 Aug 8|
|Event||14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018 - Prague, Czech Republic|
Duration: 2018 Jul 2 → 2018 Jul 5
|Name||PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics|
|Other||14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018|
|Period||18/7/2 → 18/7/5|
Bibliographical notePublisher Copyright:
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials