TY - GEN
T1 - Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM
AU - Kim, Suk Min
AU - Song, Byungkyu
AU - Oh, Tae Woo
AU - Jung, Seong Ook
N1 - Publisher Copyright:
© 2018 IEEE.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2018/8/8
Y1 - 2018/8/8
N2 - Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.
AB - Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.
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U2 - 10.1109/PRIME.2018.8430359
DO - 10.1109/PRIME.2018.8430359
M3 - Conference contribution
AN - SCOPUS:85052495935
SN - 9781538653869
T3 - PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics
SP - 65
EP - 68
BT - PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018
Y2 - 2 July 2018 through 5 July 2018
ER -