Analytical model of short-channel double-gate JFETs

Jiwon Chang, Ashok K. Kapoor, Leonard F. Register, Sanjay K. Banerjee

Research output: Contribution to journalArticlepeer-review

28 Citations (Scopus)

Abstract

In this paper, we propose a compact model of the short-channel double-gate (DG) JFETs, which are devices intended for low-power logic applications. In order to make the current equation continuous through all operating conditions from the subthreshold to well above the threshold without nonphysical fitting parameters, mobile carriers in depletion regions are considered. For describing the short-channel behavior, relevant parameters extracted from the 2-D analytical solution of Poisson's equation are used to modify long-channel equations. The field-dependent mobility, velocity saturation, channel-length modulation, and drain-induced barrier lowering are considered in the short-channel analysis. Models for the DG JFET are verified through numerically simulated currentvoltage characteristics. Based on the model of the DG JFETs, the advantages of the DG JFETs over single-gate MOSFETswhich may have similar fabrication requirementswith the subthreshold regime are addressed.

Original languageEnglish
Article number5497123
Pages (from-to)1846-1855
Number of pages10
JournalIEEE Transactions on Electron Devices
Volume57
Issue number8
DOIs
Publication statusPublished - 2010 Aug

Bibliographical note

Funding Information:
Dr. Kapoor is a member of the IEEE Electron Devices Society, Material Research Society, and Sigma Xi. He was the recipient of the Inventor of the Year Award from LSI Logic in 1995.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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