Abstract
Instruction prefetching methods are analyzed using a cache performance model. Improvement in performance achieved by using an instruction prefetching method is classified into two factors: the number of cache misses reduced by prefetching and the average amount of miss penalty reduced by successful prefetches. Conventional instruction prefetching methods are analyzed based on these two factors. Results show that the amount of miss penalty reduced by successful prefetches, called prefetch efficiency, is more crucial in obtaining a significant improvement in performance than the number of cache misses reduced by a given prefetching method. The effectiveness and limitations of conventional methods used to increase prefetch efficiency are examined using the analytical model and simulation. The analysis reveals that any effective instruction prefetching technique should be designed by utilizing the architectural characteristics of the underlying memory system as an important fundamental direction to achieve significant performance improvement required for future high performance systems.
| Original language | English |
|---|---|
| Pages (from-to) | 501-508 |
| Number of pages | 8 |
| Journal | IEEE International Performance, Computing and Communications Conference, Proceedings |
| Publication status | Published - 2000 Jan 1 |
| Event | IEEE International Performance, Computing, and Communications Conference (IPCCC 2000) - Phoenix, AZ, USA Duration: 2000 Feb 20 → 2000 Feb 22 |
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All Science Journal Classification (ASJC) codes
- Media Technology
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Analyzing instruction prefetching techniques via a cache performance model : Effectiveness and limitations. / Park, Gi Ho; Han, Tack Don; Kim, Shin Dug.
In: IEEE International Performance, Computing and Communications Conference, Proceedings, 01.01.2000, p. 501-508.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - Analyzing instruction prefetching techniques via a cache performance model
T2 - Effectiveness and limitations
AU - Park, Gi Ho
AU - Han, Tack Don
AU - Kim, Shin Dug
PY - 2000/1/1
Y1 - 2000/1/1
N2 - Instruction prefetching methods are analyzed using a cache performance model. Improvement in performance achieved by using an instruction prefetching method is classified into two factors: the number of cache misses reduced by prefetching and the average amount of miss penalty reduced by successful prefetches. Conventional instruction prefetching methods are analyzed based on these two factors. Results show that the amount of miss penalty reduced by successful prefetches, called prefetch efficiency, is more crucial in obtaining a significant improvement in performance than the number of cache misses reduced by a given prefetching method. The effectiveness and limitations of conventional methods used to increase prefetch efficiency are examined using the analytical model and simulation. The analysis reveals that any effective instruction prefetching technique should be designed by utilizing the architectural characteristics of the underlying memory system as an important fundamental direction to achieve significant performance improvement required for future high performance systems.
AB - Instruction prefetching methods are analyzed using a cache performance model. Improvement in performance achieved by using an instruction prefetching method is classified into two factors: the number of cache misses reduced by prefetching and the average amount of miss penalty reduced by successful prefetches. Conventional instruction prefetching methods are analyzed based on these two factors. Results show that the amount of miss penalty reduced by successful prefetches, called prefetch efficiency, is more crucial in obtaining a significant improvement in performance than the number of cache misses reduced by a given prefetching method. The effectiveness and limitations of conventional methods used to increase prefetch efficiency are examined using the analytical model and simulation. The analysis reveals that any effective instruction prefetching technique should be designed by utilizing the architectural characteristics of the underlying memory system as an important fundamental direction to achieve significant performance improvement required for future high performance systems.
UR - http://www.scopus.com/inward/record.url?scp=0033731933&partnerID=8YFLogxK
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M3 - Conference article
AN - SCOPUS:0033731933
SP - 501
EP - 508
JO - IEEE International Performance, Computing and Communications Conference, Proceedings
JF - IEEE International Performance, Computing and Communications Conference, Proceedings
SN - 1097-2641
ER -