Application-Adaptive Intelligent Cache Memory System

Jung Hoon Lee, Shin-Dug Kim, Charles Weems

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

This article presents the design of a simple hardware-controlled, high performance cache system. The design supports fast access time, optimal utilization of temporal and spatial localities adaptive to given applications, and a simple dynamic fetching mechanism with different fetch sizes. Support for dynamically varying the fetch size makes the cache equally effective for general-purpose as well as multimedia applications. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with twice as much space. The average miss ratio, compared with the victim cache with 32-byte block size, is improved by about 41% or 60% for general applications and multimedia applications, respectively. It is also shown that power consumption of the proposed cache is around 10% to 60% lower than other cache systems that we examine. Our cache system thus offers high performance with low power consumption and low hardware cost.

Original languageEnglish
Pages (from-to)56-78
Number of pages23
JournalACM Transactions on Embedded Computing Systems
Volume1
Issue number1
DOIs
Publication statusPublished - 2002 Jan 1

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Cache memory
Electric power utilization
Hardware
Data storage equipment
Costs

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

Cite this

@article{9237b9fe185b45e2b0a1eea9c712ec7d,
title = "Application-Adaptive Intelligent Cache Memory System",
abstract = "This article presents the design of a simple hardware-controlled, high performance cache system. The design supports fast access time, optimal utilization of temporal and spatial localities adaptive to given applications, and a simple dynamic fetching mechanism with different fetch sizes. Support for dynamically varying the fetch size makes the cache equally effective for general-purpose as well as multimedia applications. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with twice as much space. The average miss ratio, compared with the victim cache with 32-byte block size, is improved by about 41{\%} or 60{\%} for general applications and multimedia applications, respectively. It is also shown that power consumption of the proposed cache is around 10{\%} to 60{\%} lower than other cache systems that we examine. Our cache system thus offers high performance with low power consumption and low hardware cost.",
author = "Lee, {Jung Hoon} and Shin-Dug Kim and Charles Weems",
year = "2002",
month = "1",
day = "1",
doi = "10.1145/581888.581893",
language = "English",
volume = "1",
pages = "56--78",
journal = "Transactions on Embedded Computing Systems",
issn = "1539-9087",
publisher = "Association for Computing Machinery (ACM)",
number = "1",

}

Application-Adaptive Intelligent Cache Memory System. / Lee, Jung Hoon; Kim, Shin-Dug; Weems, Charles.

In: ACM Transactions on Embedded Computing Systems, Vol. 1, No. 1, 01.01.2002, p. 56-78.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Application-Adaptive Intelligent Cache Memory System

AU - Lee, Jung Hoon

AU - Kim, Shin-Dug

AU - Weems, Charles

PY - 2002/1/1

Y1 - 2002/1/1

N2 - This article presents the design of a simple hardware-controlled, high performance cache system. The design supports fast access time, optimal utilization of temporal and spatial localities adaptive to given applications, and a simple dynamic fetching mechanism with different fetch sizes. Support for dynamically varying the fetch size makes the cache equally effective for general-purpose as well as multimedia applications. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with twice as much space. The average miss ratio, compared with the victim cache with 32-byte block size, is improved by about 41% or 60% for general applications and multimedia applications, respectively. It is also shown that power consumption of the proposed cache is around 10% to 60% lower than other cache systems that we examine. Our cache system thus offers high performance with low power consumption and low hardware cost.

AB - This article presents the design of a simple hardware-controlled, high performance cache system. The design supports fast access time, optimal utilization of temporal and spatial localities adaptive to given applications, and a simple dynamic fetching mechanism with different fetch sizes. Support for dynamically varying the fetch size makes the cache equally effective for general-purpose as well as multimedia applications. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with twice as much space. The average miss ratio, compared with the victim cache with 32-byte block size, is improved by about 41% or 60% for general applications and multimedia applications, respectively. It is also shown that power consumption of the proposed cache is around 10% to 60% lower than other cache systems that we examine. Our cache system thus offers high performance with low power consumption and low hardware cost.

UR - http://www.scopus.com/inward/record.url?scp=55849135721&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=55849135721&partnerID=8YFLogxK

U2 - 10.1145/581888.581893

DO - 10.1145/581888.581893

M3 - Article

AN - SCOPUS:55849135721

VL - 1

SP - 56

EP - 78

JO - Transactions on Embedded Computing Systems

JF - Transactions on Embedded Computing Systems

SN - 1539-9087

IS - 1

ER -