Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory

Heechai Kang, Jisu Kim, Hanwool Jeong, Young Hwi Yang, Seong Ook Jung

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

We prove analytically that the yield of static random access memory (SRAM) is intrinsically a function of its architecture owing to the correlation among cell failures. In addition, architecture-aware analytical yield models are proposed for read access. The yield results using the proposed models show that the most dominant factor determining yield is the variation in the voltage difference between bitlines due to the cell leakage current variation according to the SRAM architecture. The models also show the possibility that the most dominant factor determining the yield can change with the relative ratios among the amounts of changes in the correlation, recovery sample space, distributions of the sense amplifier enable time, voltage difference between bitlines, as well as sense amplifier offset voltage, memory capacity, and redundancy scheme. The proposed yield models show that combined row and column redundancy ensures the highest yield, whereas column redundancy is the most efficient.

Original languageEnglish
Article number6822613
Pages (from-to)752-765
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number4
DOIs
Publication statusPublished - 2015 Apr 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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