Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory

Heechai Kang, Jisu Kim, Hanwool Jeong, Young Hwi Yang, Seong Ook Jung

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

We prove analytically that the yield of static random access memory (SRAM) is intrinsically a function of its architecture owing to the correlation among cell failures. In addition, architecture-aware analytical yield models are proposed for read access. The yield results using the proposed models show that the most dominant factor determining yield is the variation in the voltage difference between bitlines due to the cell leakage current variation according to the SRAM architecture. The models also show the possibility that the most dominant factor determining the yield can change with the relative ratios among the amounts of changes in the correlation, recovery sample space, distributions of the sense amplifier enable time, voltage difference between bitlines, as well as sense amplifier offset voltage, memory capacity, and redundancy scheme. The proposed yield models show that combined row and column redundancy ensures the highest yield, whereas column redundancy is the most efficient.

Original languageEnglish
Article number6822613
Pages (from-to)752-765
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number4
DOIs
Publication statusPublished - 2015 Apr 1

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Redundancy
Data storage equipment
Electric potential
Memory architecture
Leakage currents
Recovery

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

@article{40e793a8aae441548f087379c79b5e61,
title = "Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory",
abstract = "We prove analytically that the yield of static random access memory (SRAM) is intrinsically a function of its architecture owing to the correlation among cell failures. In addition, architecture-aware analytical yield models are proposed for read access. The yield results using the proposed models show that the most dominant factor determining yield is the variation in the voltage difference between bitlines due to the cell leakage current variation according to the SRAM architecture. The models also show the possibility that the most dominant factor determining the yield can change with the relative ratios among the amounts of changes in the correlation, recovery sample space, distributions of the sense amplifier enable time, voltage difference between bitlines, as well as sense amplifier offset voltage, memory capacity, and redundancy scheme. The proposed yield models show that combined row and column redundancy ensures the highest yield, whereas column redundancy is the most efficient.",
author = "Heechai Kang and Jisu Kim and Hanwool Jeong and Yang, {Young Hwi} and Jung, {Seong Ook}",
year = "2015",
month = "4",
day = "1",
doi = "10.1109/TVLSI.2014.2321897",
language = "English",
volume = "23",
pages = "752--765",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory. / Kang, Heechai; Kim, Jisu; Jeong, Hanwool; Yang, Young Hwi; Jung, Seong Ook.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 4, 6822613, 01.04.2015, p. 752-765.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory

AU - Kang, Heechai

AU - Kim, Jisu

AU - Jeong, Hanwool

AU - Yang, Young Hwi

AU - Jung, Seong Ook

PY - 2015/4/1

Y1 - 2015/4/1

N2 - We prove analytically that the yield of static random access memory (SRAM) is intrinsically a function of its architecture owing to the correlation among cell failures. In addition, architecture-aware analytical yield models are proposed for read access. The yield results using the proposed models show that the most dominant factor determining yield is the variation in the voltage difference between bitlines due to the cell leakage current variation according to the SRAM architecture. The models also show the possibility that the most dominant factor determining the yield can change with the relative ratios among the amounts of changes in the correlation, recovery sample space, distributions of the sense amplifier enable time, voltage difference between bitlines, as well as sense amplifier offset voltage, memory capacity, and redundancy scheme. The proposed yield models show that combined row and column redundancy ensures the highest yield, whereas column redundancy is the most efficient.

AB - We prove analytically that the yield of static random access memory (SRAM) is intrinsically a function of its architecture owing to the correlation among cell failures. In addition, architecture-aware analytical yield models are proposed for read access. The yield results using the proposed models show that the most dominant factor determining yield is the variation in the voltage difference between bitlines due to the cell leakage current variation according to the SRAM architecture. The models also show the possibility that the most dominant factor determining the yield can change with the relative ratios among the amounts of changes in the correlation, recovery sample space, distributions of the sense amplifier enable time, voltage difference between bitlines, as well as sense amplifier offset voltage, memory capacity, and redundancy scheme. The proposed yield models show that combined row and column redundancy ensures the highest yield, whereas column redundancy is the most efficient.

UR - http://www.scopus.com/inward/record.url?scp=85028140272&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85028140272&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2014.2321897

DO - 10.1109/TVLSI.2014.2321897

M3 - Article

VL - 23

SP - 752

EP - 765

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 4

M1 - 6822613

ER -