Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM

Janghee Lee, Seongjoo Lee, Jaeseok Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

a We propose a new architecture of fast symbol timing synchronization system which consists of a received signal power detector, a correlation power detector and a peak detector. These blocks have some shared hardware blocks to reduce the hardware complexity. A two-step peak detection hardware architecture is proposed to acquire the symbol timing synchronization. The proposed design can detect the correct FFT starting point within three symbols using the first two reference symbols in wireless ATM. Consequently, the proposed system is very useful for burst data transmission in wireless LAN or wireless ATM systems. The proposed architecture is designed and verified in VHDL.

Original languageEnglish
Title of host publicationIEEE Region 10 Annual International Conference, Proceedings/TENCON
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages301-304
Number of pages4
ISBN (Electronic)0780357396, 9780780357396
DOIs
Publication statusPublished - 1999 Jan 1
Event1999 IEEE Region 10 Conference, TENCON 1999 - Cheju Island, Korea, Republic of
Duration: 1999 Sep 151999 Sep 17

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON
Volume1
ISSN (Print)2159-3442
ISSN (Electronic)2159-3450

Other

Other1999 IEEE Region 10 Conference, TENCON 1999
CountryKorea, Republic of
CityCheju Island
Period99/9/1599/9/17

Fingerprint

Automatic teller machines
Synchronization
Detectors
Hardware
Computer hardware description languages
Local area networks
Fast Fourier transforms
Data communication systems
Computer systems

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Lee, J., Lee, S., & Kim, J. (1999). Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. In IEEE Region 10 Annual International Conference, Proceedings/TENCON (pp. 301-304). (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TENCON.1999.818410
Lee, Janghee ; Lee, Seongjoo ; Kim, Jaeseok. / Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. IEEE Region 10 Annual International Conference, Proceedings/TENCON. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 301-304 (IEEE Region 10 Annual International Conference, Proceedings/TENCON).
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Lee, J, Lee, S & Kim, J 1999, Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. in IEEE Region 10 Annual International Conference, Proceedings/TENCON. IEEE Region 10 Annual International Conference, Proceedings/TENCON, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 301-304, 1999 IEEE Region 10 Conference, TENCON 1999, Cheju Island, Korea, Republic of, 99/9/15. https://doi.org/10.1109/TENCON.1999.818410

Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. / Lee, Janghee; Lee, Seongjoo; Kim, Jaeseok.

IEEE Region 10 Annual International Conference, Proceedings/TENCON. Institute of Electrical and Electronics Engineers Inc., 1999. p. 301-304 (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - a We propose a new architecture of fast symbol timing synchronization system which consists of a received signal power detector, a correlation power detector and a peak detector. These blocks have some shared hardware blocks to reduce the hardware complexity. A two-step peak detection hardware architecture is proposed to acquire the symbol timing synchronization. The proposed design can detect the correct FFT starting point within three symbols using the first two reference symbols in wireless ATM. Consequently, the proposed system is very useful for burst data transmission in wireless LAN or wireless ATM systems. The proposed architecture is designed and verified in VHDL.

AB - a We propose a new architecture of fast symbol timing synchronization system which consists of a received signal power detector, a correlation power detector and a peak detector. These blocks have some shared hardware blocks to reduce the hardware complexity. A two-step peak detection hardware architecture is proposed to acquire the symbol timing synchronization. The proposed design can detect the correct FFT starting point within three symbols using the first two reference symbols in wireless ATM. Consequently, the proposed system is very useful for burst data transmission in wireless LAN or wireless ATM systems. The proposed architecture is designed and verified in VHDL.

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Lee J, Lee S, Kim J. Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. In IEEE Region 10 Annual International Conference, Proceedings/TENCON. Institute of Electrical and Electronics Engineers Inc. 1999. p. 301-304. (IEEE Region 10 Annual International Conference, Proceedings/TENCON). https://doi.org/10.1109/TENCON.1999.818410