Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM

Janghee Lee, Seongjoo Lee, Jaeseok Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

a We propose a new architecture of fast symbol timing synchronization system which consists of a received signal power detector, a correlation power detector and a peak detector. These blocks have some shared hardware blocks to reduce the hardware complexity. A two-step peak detection hardware architecture is proposed to acquire the symbol timing synchronization. The proposed design can detect the correct FFT starting point within three symbols using the first two reference symbols in wireless ATM. Consequently, the proposed system is very useful for burst data transmission in wireless LAN or wireless ATM systems. The proposed architecture is designed and verified in VHDL.

Original languageEnglish
Title of host publicationIEEE Region 10 Annual International Conference, Proceedings/TENCON
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages301-304
Number of pages4
ISBN (Electronic)0780357396, 9780780357396
DOIs
Publication statusPublished - 1999
Event1999 IEEE Region 10 Conference, TENCON 1999 - Cheju Island, Korea, Republic of
Duration: 1999 Sep 151999 Sep 17

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON
Volume1
ISSN (Print)2159-3442
ISSN (Electronic)2159-3450

Other

Other1999 IEEE Region 10 Conference, TENCON 1999
CountryKorea, Republic of
CityCheju Island
Period99/9/1599/9/17

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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