Area-efficient and low-power implementation of vision chips using multi-level mixed-mode processing

Jihyun Cho, Seokjun Park, Jaehyuk Choi, Euisik Yoon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Miniaturized low-power implementation of a vision system is critical in battery-operated systems such as wireless sensor network (WSN), micro-air-vehicles (MAV), and mobile phones. Conventional digital-intensive processing uses the raw image with huge redundancy which degrades the power and speed. This paper reports multi-level mixed-mode processing schemes for efficient VLSI implementation in terms of power, area and speed. In this approach, the processing is distributed in pixel-level, column-level and chip-level processors. Each processor operates in mixed-mode, analog and digital, domains for an optimal use of resources. Three vision chips have been designed and characterized to show the effectiveness of this approach. First, motion detection and feature extraction are implemented in an object-adaptive CMOS image sensor to remove temporal and spatial redundancies for low power operation. Second, a neuromorphic algorithm is implemented for optic flow generation in mixed-mode circuits. Event-driven analog processing units allow low power operation of pre-processing, while the digital processor provides the robustness of backend processing. Finally, background light subtraction is implemented in a 3-D camera for outdoors mobile applications. The reconfigurable pixel array implemented by pixel-merging and super-resolution could achieve faster processing and better background light suppression.

Original languageEnglish
Title of host publicationInternational Workshop on Cellular Nanoscale Networks and their Applications
EditorsMichael Niemier, Wolfgang Porod
PublisherIEEE Computer Society
ISBN (Electronic)9781479964680
DOIs
Publication statusPublished - 2014 Aug 29
Event2014 14th International Workshop on Cellular Nanoscale Networks and Their Applications, CNNA 2014 - Notre Dame, United States
Duration: 2014 Jul 292014 Jul 31

Publication series

NameInternational Workshop on Cellular Nanoscale Networks and their Applications
ISSN (Print)2165-0160
ISSN (Electronic)2165-0179

Conference

Conference2014 14th International Workshop on Cellular Nanoscale Networks and Their Applications, CNNA 2014
CountryUnited States
CityNotre Dame
Period14/7/2914/7/31

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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    Cho, J., Park, S., Choi, J., & Yoon, E. (2014). Area-efficient and low-power implementation of vision chips using multi-level mixed-mode processing. In M. Niemier, & W. Porod (Eds.), International Workshop on Cellular Nanoscale Networks and their Applications [6888638] (International Workshop on Cellular Nanoscale Networks and their Applications). IEEE Computer Society. https://doi.org/10.1109/CNNA.2014.6888638