Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure

Youngki Moon; Hyunho Yoo; Donghyun Han; Sungho Kang

doi:10.1109/ISOCC53507.2021.9613937

Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure

Youngki Moon, Hyunho Yoo, Donghyun Han, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Built in redundancy analysis (BIRA) with the various spare structure is proposed to achieve higher memory yield [1]. However, various spare structures have caused the large hardware overhead. In this paper, an area efficient BIRA is proposed which uses separate CAMs for fault collection to reduce the hardware overhead and the pre-solutions searching the most appropriate addresses of various spares for redundancy analysis. The experimental results show that the proposed BIRA can achieve the higher repair rate compared to the previous works.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	431-432
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613937
Publication status	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/10/6 → 21/10/9

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NO. 2019R1A2C3011079).

Publisher Copyright:
© 2021 IEEE.

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Information Systems
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC53507.2021.9613937

Cite this

Moon, Y., Yoo, H., Han, D., & Kang, S. (2021). Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 431-432). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613937

@inproceedings{d33b8517d19646cda70c125b6135fe42,

title = "Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure",

abstract = "Built in redundancy analysis (BIRA) with the various spare structure is proposed to achieve higher memory yield [1]. However, various spare structures have caused the large hardware overhead. In this paper, an area efficient BIRA is proposed which uses separate CAMs for fault collection to reduce the hardware overhead and the pre-solutions searching the most appropriate addresses of various spares for redundancy analysis. The experimental results show that the proposed BIRA can achieve the higher repair rate compared to the previous works.",

author = "Youngki Moon and Hyunho Yoo and Donghyun Han and Sungho Kang",

note = "Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NO. 2019R1A2C3011079). Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613937",

language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "431--432",

booktitle = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

address = "United States",

}

Moon, Y, Yoo, H, Han, D & Kang, S 2021, Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 431-432, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 21/10/6. https://doi.org/10.1109/ISOCC53507.2021.9613937

Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure. / Moon, Youngki; Yoo, Hyunho; Han, Donghyun et al.

Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 431-432 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure

AU - Moon, Youngki

AU - Yoo, Hyunho

AU - Han, Donghyun

AU - Kang, Sungho

N1 - Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NO. 2019R1A2C3011079). Publisher Copyright: © 2021 IEEE.

PY - 2021

Y1 - 2021

N2 - Built in redundancy analysis (BIRA) with the various spare structure is proposed to achieve higher memory yield [1]. However, various spare structures have caused the large hardware overhead. In this paper, an area efficient BIRA is proposed which uses separate CAMs for fault collection to reduce the hardware overhead and the pre-solutions searching the most appropriate addresses of various spares for redundancy analysis. The experimental results show that the proposed BIRA can achieve the higher repair rate compared to the previous works.

AB - Built in redundancy analysis (BIRA) with the various spare structure is proposed to achieve higher memory yield [1]. However, various spare structures have caused the large hardware overhead. In this paper, an area efficient BIRA is proposed which uses separate CAMs for fault collection to reduce the hardware overhead and the pre-solutions searching the most appropriate addresses of various spares for redundancy analysis. The experimental results show that the proposed BIRA can achieve the higher repair rate compared to the previous works.

UR - http://www.scopus.com/inward/record.url?scp=85123347172&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85123347172&partnerID=8YFLogxK

U2 - 10.1109/ISOCC53507.2021.9613937

DO - 10.1109/ISOCC53507.2021.9613937

M3 - Conference contribution

AN - SCOPUS:85123347172

T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021

SP - 431

EP - 432

BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th International System-on-Chip Design Conference, ISOCC 2021

Y2 - 6 October 2021 through 9 October 2021

ER -

Moon Y, Yoo H, Han D, Kang S. Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure. In Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 431-432. (Proceedings - International SoC Design Conference 2021, ISOCC 2021). doi: 10.1109/ISOCC53507.2021.9613937

Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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