An area-efficient correlated double sampling (CDS) circuit is proposed. In conventional designs, most of the area of CDS circuits is occupied by two large on-chip sampling capacitors. A new CDS scheme is devised using only one sampling capacitor. The proposed CDS circuit has been successfully realised in a small two column pitch of 7.2m in a test chip fabricated using 0.18m CMOS process and has demonstrated fixed pattern noise less than 0.46.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering