Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors

S. W. Han; E. Yoon

doi:10.1049/el:20064189

Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors

S. W. Han, E. Yoon

Yonsei-IBS Institute

Research output: Contribution to journal › Article

21 Citations (Scopus)

Abstract

An area-efficient correlated double sampling (CDS) circuit is proposed. In conventional designs, most of the area of CDS circuits is occupied by two large on-chip sampling capacitors. A new CDS scheme is devised using only one sampling capacitor. The proposed CDS circuit has been successfully realised in a small two column pitch of 7.2m in a test chip fabricated using 0.18m CMOS process and has demonstrated fixed pattern noise less than 0.46.

Original language	English
Pages (from-to)	335-337
Number of pages	3
Journal	Electronics Letters
Volume	42
Issue number	6
DOIs	https://doi.org/10.1049/el:20064189
Publication status	Published - 2006 Mar 16

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el:20064189

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Han, S. W., & Yoon, E. (2006). Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors. Electronics Letters, 42(6), 335-337. https://doi.org/10.1049/el:20064189

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