Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors

S. W. Han, E. Yoon

Research output: Contribution to journalArticle

21 Citations (Scopus)

Abstract

An area-efficient correlated double sampling (CDS) circuit is proposed. In conventional designs, most of the area of CDS circuits is occupied by two large on-chip sampling capacitors. A new CDS scheme is devised using only one sampling capacitor. The proposed CDS circuit has been successfully realised in a small two column pitch of 7.2m in a test chip fabricated using 0.18m CMOS process and has demonstrated fixed pattern noise less than 0.46.

Original languageEnglish
Pages (from-to)335-337
Number of pages3
JournalElectronics Letters
Volume42
Issue number6
DOIs
Publication statusPublished - 2006 Mar 16

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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