Area-optimal sensing circuit designs in deep submicrometer STT-RAM

Sara Choi, Taehui Na, Seong Ook Jung, Jung Pill Kim, Seung H. Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.

Original languageEnglish
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1246-1249
Number of pages4
Volume2016-July
ISBN (Electronic)9781479953400
DOIs
Publication statusPublished - 2016 Jul 29
Event2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
Duration: 2016 May 222016 May 25

Other

Other2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
CountryCanada
CityMontreal
Period16/5/2216/5/25

Fingerprint

Torque
Data storage equipment
Networks (circuits)
Threshold voltage
Capacitance

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Choi, S., Na, T., Jung, S. O., Kim, J. P., & Kang, S. H. (2016). Area-optimal sensing circuit designs in deep submicrometer STT-RAM. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (Vol. 2016-July, pp. 1246-1249). [7527473] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2016.7527473
Choi, Sara ; Na, Taehui ; Jung, Seong Ook ; Kim, Jung Pill ; Kang, Seung H. / Area-optimal sensing circuit designs in deep submicrometer STT-RAM. ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July Institute of Electrical and Electronics Engineers Inc., 2016. pp. 1246-1249
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Choi, S, Na, T, Jung, SO, Kim, JP & Kang, SH 2016, Area-optimal sensing circuit designs in deep submicrometer STT-RAM. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems. vol. 2016-July, 7527473, Institute of Electrical and Electronics Engineers Inc., pp. 1246-1249, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 16/5/22. https://doi.org/10.1109/ISCAS.2016.7527473

Area-optimal sensing circuit designs in deep submicrometer STT-RAM. / Choi, Sara; Na, Taehui; Jung, Seong Ook; Kim, Jung Pill; Kang, Seung H.

ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July Institute of Electrical and Electronics Engineers Inc., 2016. p. 1246-1249 7527473.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Choi S, Na T, Jung SO, Kim JP, Kang SH. Area-optimal sensing circuit designs in deep submicrometer STT-RAM. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July. Institute of Electrical and Electronics Engineers Inc. 2016. p. 1246-1249. 7527473 https://doi.org/10.1109/ISCAS.2016.7527473