As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.
|Title of host publication||ISCAS 2016 - IEEE International Symposium on Circuits and Systems|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2016 Jul 29|
|Event||2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada|
Duration: 2016 May 22 → 2016 May 25
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Other||2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016|
|Period||16/5/22 → 16/5/25|
Bibliographical notePublisher Copyright:
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering