Asymmetric ECC organization in 3D-memory via spare column utilization

Hyunseung Han; Joon Sung Yang

doi:10.1109/DFT.2015.7315128

Asymmetric ECC organization in 3D-memory via spare column utilization

Hyunseung Han, Joon Sung Yang

College of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.

Original language	English
Title of host publication	Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	13-16
Number of pages	4
ISBN (Electronic)	9781509003129
DOIs	https://doi.org/10.1109/DFT.2015.7315128
Publication status	Published - 2015 Nov 2
Event	28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 - Amherst, United States Duration: 2015 Oct 12 → 2015 Oct 14

Publication series

Name	Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015

Conference

Conference	28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
Country	United States
City	Amherst
Period	15/10/12 → 15/10/14

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/DFT.2015.7315128

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Han, H., & Yang, J. S. (2015). Asymmetric ECC organization in 3D-memory via spare column utilization. In Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 (pp. 13-16). [7315128] (Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2015.7315128

Han, Hyunseung ; Yang, Joon Sung. / Asymmetric ECC organization in 3D-memory via spare column utilization. Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 13-16 (Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015).

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title = "Asymmetric ECC organization in 3D-memory via spare column utilization",

abstract = "3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.",

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Han, H & Yang, JS 2015, Asymmetric ECC organization in 3D-memory via spare column utilization. in Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015., 7315128, Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, Institute of Electrical and Electronics Engineers Inc., pp. 13-16, 28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, Amherst, United States, 15/10/12. https://doi.org/10.1109/DFT.2015.7315128

Asymmetric ECC organization in 3D-memory via spare column utilization. / Han, Hyunseung; Yang, Joon Sung.

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 13-16 7315128 (Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - 3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.

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Han H, Yang JS. Asymmetric ECC organization in 3D-memory via spare column utilization. In Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 13-16. 7315128. (Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015). https://doi.org/10.1109/DFT.2015.7315128