Asymmetric ECC organization in 3D-memory via spare column utilization

Hyunseung Han, Joon Sung Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.

Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages13-16
Number of pages4
ISBN (Electronic)9781509003129
DOIs
Publication statusPublished - 2015 Nov 2
Event28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 - Amherst, United States
Duration: 2015 Oct 122015 Oct 14

Publication series

NameProceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015

Conference

Conference28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
CountryUnited States
CityAmherst
Period15/10/1215/10/14

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Han, H., & Yang, J. S. (2015). Asymmetric ECC organization in 3D-memory via spare column utilization. In Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 (pp. 13-16). [7315128] (Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2015.7315128