Asymmetric ECC organization in 3D-memory via spare column utilization

Hyunseung Han; Joon Sung Yang

doi:10.1109/DFT.2015.7315128

Asymmetric ECC organization in 3D-memory via spare column utilization

Hyunseung Han, Joon Sung Yang

College of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.

Original language	English
Title of host publication	Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	13-16
Number of pages	4
ISBN (Electronic)	9781509003129
DOIs	https://doi.org/10.1109/DFT.2015.7315128
Publication status	Published - 2015 Nov 2
Event	28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 - Amherst, United States Duration: 2015 Oct 12 → 2015 Oct 14

Publication series

Name	Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015

Conference

Conference	28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
Country/Territory	United States
City	Amherst
Period	15/10/12 → 15/10/14

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/DFT.2015.7315128

Cite this

Han, H., & Yang, J. S. (2015). Asymmetric ECC organization in 3D-memory via spare column utilization. In Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 (pp. 13-16). [7315128] (Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2015.7315128

Han, Hyunseung ; Yang, Joon Sung. / Asymmetric ECC organization in 3D-memory via spare column utilization. Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 13-16 (Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015).

@inproceedings{3ee7cb3aeb7d4d7190f6a295a2c8c8bb,

title = "Asymmetric ECC organization in 3D-memory via spare column utilization",

abstract = "3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.",

author = "Hyunseung Han and Yang, {Joon Sung}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 ; Conference date: 12-10-2015 Through 14-10-2015",

year = "2015",

month = nov,

day = "2",

doi = "10.1109/DFT.2015.7315128",

language = "English",

series = "Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "13--16",

booktitle = "Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015",

address = "United States",

}

Han, H & Yang, JS 2015, Asymmetric ECC organization in 3D-memory via spare column utilization. in Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015., 7315128, Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, Institute of Electrical and Electronics Engineers Inc., pp. 13-16, 28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, Amherst, United States, 15/10/12. https://doi.org/10.1109/DFT.2015.7315128

Asymmetric ECC organization in 3D-memory via spare column utilization. / Han, Hyunseung; Yang, Joon Sung.

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 13-16 7315128 (Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Asymmetric ECC organization in 3D-memory via spare column utilization

AU - Han, Hyunseung

AU - Yang, Joon Sung

PY - 2015/11/2

Y1 - 2015/11/2

N2 - 3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.

AB - 3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.

UR - http://www.scopus.com/inward/record.url?scp=84962787244&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84962787244&partnerID=8YFLogxK

U2 - 10.1109/DFT.2015.7315128

DO - 10.1109/DFT.2015.7315128

M3 - Conference contribution

AN - SCOPUS:84962787244

T3 - Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015

SP - 13

EP - 16

BT - Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015

Y2 - 12 October 2015 through 14 October 2015

ER -

Han H, Yang JS. Asymmetric ECC organization in 3D-memory via spare column utilization. In Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 13-16. 7315128. (Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015). https://doi.org/10.1109/DFT.2015.7315128

Asymmetric ECC organization in 3D-memory via spare column utilization

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this