3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.
|Title of host publication||Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2015 Nov 2|
|Event||28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 - Amherst, United States|
Duration: 2015 Oct 12 → 2015 Oct 14
|Name||Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015|
|Conference||28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015|
|Period||15/10/12 → 15/10/14|
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality