Prefetching is one of the main techniques for improving the performance of modern processors. Various prefetch algorithms have been proposed targeting various applications and memory access patterns. Modern SoCs are mainly equipped with multicore processors, and various processes are operated separately by each core. This implies that for each core, different prefetcher may work better. In this paper, we propose a hardware prefetcher that integrates three prefetching algorithms and statically allocates a prefetching algorithm that provides better performance to each workload in a multicore processor. We observe 4.6% overall performance improvement compared to using a single prefetcher and reduce buffer resources by 41%.
|Title of host publication||Proceedings - International SoC Design Conference, ISOCC 2020|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2020 Oct 21|
|Event||17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of|
Duration: 2020 Oct 21 → 2020 Oct 24
|Name||Proceedings - International SoC Design Conference, ISOCC 2020|
|Conference||17th International System-on-Chip Design Conference, ISOCC 2020|
|Country||Korea, Republic of|
|Period||20/10/21 → 20/10/24|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This research was supported by R&D program for advanced integrated-intelligence for identification through the National Research Foundation of Korea(NRF) funded by Ministry of Trade, Industry and Energy (2018M3E3A1057248), And the chip fabrication and EDA Tool were supported by the IC Design Education Center.
© 2020 IEEE.
All Science Journal Classification (ASJC) codes
- Energy Engineering and Power Technology
- Electrical and Electronic Engineering
- Artificial Intelligence
- Hardware and Architecture