Asymmetric slew logic threshold method on near threshold region

Cell operation in the Near Threshold Voltage (NTV) domain is attracting attention as one of the circuit level low-power implementations circuit. In this domain, cell operation has large delay characteristic compared to Super Threshold Voltage (STV) environment but has high energy efficiency. In order to utilize circuit that operate in Near Threshold Voltage domain, supporting of Computer-Aided Design(CAD) is essential. There are many recently work about design methodology to apply NTV circuit. Although design methodology exploration in the NTV area has been actively studied, it is difficult to immediately commercialize the research at CAD flow due to modified design methodology. In this work, we propose asymmetric slew logic threshold optimization on NTV without modifying CAD flow. Our proposed approach achieves 9.07%, 11.30% and 9.06% improvement in accuracy in stage delay, stage slew and path delay, respectively, compared to the existing symmetric slew logic threshold method.