At-speed boundary-scan interconnect testing in a board with multiple system clocks

Jongchul Shin, Hyunjin Kim, Sungho Kang

Research output: Contribution to journalConference articlepeer-review

9 Citations (Scopus)


As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-defined register is proposed. Test methods based on the new architecture can accomplish cost-effective at-speed testing and propagation delay measurements on board-level interconnects. Particularly when the board under test has multiple domains of interconnects controlled by different clock speeds, our at-speed solution is much more efficient than other previous works.

Original languageEnglish
Article number761168
Pages (from-to)473-477
Number of pages5
JournalProceedings -Design, Automation and Test in Europe, DATE
Publication statusPublished - 1999
EventDesign, Automation and Test in Europe Conference and Exhibition 1999, DATE 1999 - Munich, Germany
Duration: 1999 Mar 91999 Mar 12

All Science Journal Classification (ASJC) codes

  • Engineering(all)


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