As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-defined register is proposed. Test methods based on the new architecture can accomplish cost-effective at-speed testing and propagation delay measurements on board-level interconnects. Particularly when the board under test has multiple domains of interconnects controlled by different clock speeds, our at-speed solution is much more efficient than other previous works.
|Number of pages||5|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|Publication status||Published - 1999 Dec 1|
|Event||Design, Automation and Test in Europe Conference and Exhibition 1999, DATE 1999 - Munich, Germany|
Duration: 1999 Mar 9 → 1999 Mar 12
All Science Journal Classification (ASJC) codes