At-speed boundary-scan interconnect testing in a board with multiple system clocks

Jongchul Shin, Hyunjin Kim, Sungho Kang

Research output: Contribution to journalConference article

8 Citations (Scopus)

Abstract

As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-defined register is proposed. Test methods based on the new architecture can accomplish cost-effective at-speed testing and propagation delay measurements on board-level interconnects. Particularly when the board under test has multiple domains of interconnects controlled by different clock speeds, our at-speed solution is much more efficient than other previous works.

Original languageEnglish
Article number761168
Pages (from-to)473-477
Number of pages5
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
Publication statusPublished - 1999 Dec 1
EventDesign, Automation and Test in Europe Conference and Exhibition 1999, DATE 1999 - Munich, Germany
Duration: 1999 Mar 91999 Mar 12

Fingerprint

Clocks
Testing
Costs

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

@article{08496e197e984280b676c0144346bbd1,
title = "At-speed boundary-scan interconnect testing in a board with multiple system clocks",
abstract = "As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-defined register is proposed. Test methods based on the new architecture can accomplish cost-effective at-speed testing and propagation delay measurements on board-level interconnects. Particularly when the board under test has multiple domains of interconnects controlled by different clock speeds, our at-speed solution is much more efficient than other previous works.",
author = "Jongchul Shin and Hyunjin Kim and Sungho Kang",
year = "1999",
month = "12",
day = "1",
doi = "10.1109/DATE.1999.761168",
language = "English",
pages = "473--477",
journal = "Proceedings -Design, Automation and Test in Europe, DATE",
issn = "1530-1591",

}

At-speed boundary-scan interconnect testing in a board with multiple system clocks. / Shin, Jongchul; Kim, Hyunjin; Kang, Sungho.

In: Proceedings -Design, Automation and Test in Europe, DATE, 01.12.1999, p. 473-477.

Research output: Contribution to journalConference article

TY - JOUR

T1 - At-speed boundary-scan interconnect testing in a board with multiple system clocks

AU - Shin, Jongchul

AU - Kim, Hyunjin

AU - Kang, Sungho

PY - 1999/12/1

Y1 - 1999/12/1

N2 - As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-defined register is proposed. Test methods based on the new architecture can accomplish cost-effective at-speed testing and propagation delay measurements on board-level interconnects. Particularly when the board under test has multiple domains of interconnects controlled by different clock speeds, our at-speed solution is much more efficient than other previous works.

AB - As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-defined register is proposed. Test methods based on the new architecture can accomplish cost-effective at-speed testing and propagation delay measurements on board-level interconnects. Particularly when the board under test has multiple domains of interconnects controlled by different clock speeds, our at-speed solution is much more efficient than other previous works.

UR - http://www.scopus.com/inward/record.url?scp=39749107262&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=39749107262&partnerID=8YFLogxK

U2 - 10.1109/DATE.1999.761168

DO - 10.1109/DATE.1999.761168

M3 - Conference article

AN - SCOPUS:39749107262

SP - 473

EP - 477

JO - Proceedings -Design, Automation and Test in Europe, DATE

JF - Proceedings -Design, Automation and Test in Europe, DATE

SN - 1530-1591

M1 - 761168

ER -