Neural networks are widely used in various applications, but general neural network accelerators support only one application at a time. Therefore, information for each application, such as synaptic weights and bias data, must be loaded quickly to use multiple neural network applications. Field-programmable gate array (FPGA)-based implementation has huge performance overhead owing to low data transmission bandwidth. In order to solve this problem, this paper presents an automated FPGA-based multi-neural network accelerator generation framework that can quickly support several applications by storing neural network application data in an on-chip memory inside the FPGA. To do this, we first design a shared custom hardware accelerator that can support rapid changes in multiple target neural network applications. Then, we introduce an automated multi-neural network accelerator generation framework that performs training, weight quantization, and neural accelerator synthesis.
|Title of host publication||Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2019 Feb 22|
|Event||2018 IEEE Region 10 Conference, TENCON 2018 - Jeju, Korea, Republic of|
Duration: 2018 Oct 28 → 2018 Oct 31
|Name||IEEE Region 10 Annual International Conference, Proceedings/TENCON|
|Conference||2018 IEEE Region 10 Conference, TENCON 2018|
|Country/Territory||Korea, Republic of|
|Period||18/10/28 → 18/10/31|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP)(No.NRF-2015R1C1A1A01053844), ICT R&D program of MSIP/IITP (No.2017-0-00142), and the R&D program of MOTIE/KEIT (No.10077609).
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering