Automated selection of signals to observe for efficient silicon debug

Engineering

• Bandwidth Requirement 33%
• Constraints 33%
• Cycles 33%
• Early Detection 33%
• Error 100%
• Experimental Result 33%
• Final Set 33%
• Flip Flop Circuits 100%
• Input Vector 33%
• Malfunction 33%
• Networks (Circuits) 66%
• Observability 33%
• Sequential Circuits 33%
• Silicon 66%
• Storage Requirement 33%
• Transmission Error 33%

Computer Science

• Bandwidth Requirement 33%
• Debug 100%
• Early Detection 33%
• Experimental Result 33%
• First Bug 33%
• Flip-Flop 100%
• Integer-Linear Programming 33%
• Internal Signal 33%
• Procedures 33%
• Storage Requirement 33%
• Transmission Error 33%