Automatic error pattern generation for design error detection in a design validation simulation system

Sungho Kang, Stephen A. Szygenda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Considering the fact that simulation patterns can detect a different number of design errors, the derivation of efficient simulation patterns is important. Automatic error pattern generation is introduced to generate a set of error simulation pattern which can be used as input stimuli for design error simulation, a design validation tool which provides a measure of simulation coverage. These tools provide a solution to a long standing problem that has limited design options and design cycle time. They also can decrease design and testing costs.

Original languageEnglish
Title of host publicationProceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
PublisherIEEE Computer Society
Pages533-536
Number of pages4
ISBN (Electronic)0780307682
DOIs
Publication statusPublished - 1992 Jan 1
Event5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 - Rochester, United States
Duration: 1992 Sep 211992 Sep 25

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
CountryUnited States
CityRochester
Period92/9/2192/9/25

Fingerprint

Error detection
Testing
Costs

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kang, S., & Szygenda, S. A. (1992). Automatic error pattern generation for design error detection in a design validation simulation system. In Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 (pp. 533-536). [270205] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASIC.1992.270205
Kang, Sungho ; Szygenda, Stephen A. / Automatic error pattern generation for design error detection in a design validation simulation system. Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992. IEEE Computer Society, 1992. pp. 533-536 (Proceedings of International Conference on ASIC).
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Kang, S & Szygenda, SA 1992, Automatic error pattern generation for design error detection in a design validation simulation system. in Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992., 270205, Proceedings of International Conference on ASIC, IEEE Computer Society, pp. 533-536, 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992, Rochester, United States, 92/9/21. https://doi.org/10.1109/ASIC.1992.270205

Automatic error pattern generation for design error detection in a design validation simulation system. / Kang, Sungho; Szygenda, Stephen A.

Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992. IEEE Computer Society, 1992. p. 533-536 270205 (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Kang S, Szygenda SA. Automatic error pattern generation for design error detection in a design validation simulation system. In Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992. IEEE Computer Society. 1992. p. 533-536. 270205. (Proceedings of International Conference on ASIC). https://doi.org/10.1109/ASIC.1992.270205