Automatic verification of control logics in safety instrumented system design for chemical process industry

Jinkyung Kim; Il Moon

doi:10.1016/j.jlp.2009.06.013

Automatic verification of control logics in safety instrumented system design for chemical process industry

Jinkyung Kim, Il Moon

Department of Chemical and Biomolecular Engineering

Research output: Contribution to journal › Article

4 Citations (Scopus)

Abstract

Automatic model checking is used to determine the error-free design of the SIS (Safety Instrumented System) and to find the logical errors in the chemical processes. It proposes an automatic technique to provide and to modify the P&ID design of SIS control logics. This method can be applied to verify its correctness of SIS and to find the logical errors by synthesizing a feasible sequence automatically. This study focuses on automatic verifying and synthesizing for the design, operability and reachability of SIS control logics in chemical processes.

Original language	English
Pages (from-to)	975-980
Number of pages	6
Journal	Journal of Loss Prevention in the Process Industries
Volume	22
Issue number	6
DOIs	https://doi.org/10.1016/j.jlp.2009.06.013
Publication status	Published - 2009 Nov 1

All Science Journal Classification (ASJC) codes

Control and Systems Engineering
Food Science
Chemical Engineering(all)
Safety, Risk, Reliability and Quality
Energy Engineering and Power Technology
Management Science and Operations Research
Industrial and Manufacturing Engineering

Access to Document

10.1016/j.jlp.2009.06.013

Fingerprint Dive into the research topics of 'Automatic verification of control logics in safety instrumented system design for chemical process industry'. Together they form a unique fingerprint.

Cite this

Kim, J., & Moon, I. (2009). Automatic verification of control logics in safety instrumented system design for chemical process industry. Journal of Loss Prevention in the Process Industries, 22(6), 975-980. https://doi.org/10.1016/j.jlp.2009.06.013

@article{558736ad08324cd0a70f1620af154fd2,

title = "Automatic verification of control logics in safety instrumented system design for chemical process industry",

abstract = "Automatic model checking is used to determine the error-free design of the SIS (Safety Instrumented System) and to find the logical errors in the chemical processes. It proposes an automatic technique to provide and to modify the P&ID design of SIS control logics. This method can be applied to verify its correctness of SIS and to find the logical errors by synthesizing a feasible sequence automatically. This study focuses on automatic verifying and synthesizing for the design, operability and reachability of SIS control logics in chemical processes.",

author = "Jinkyung Kim and Il Moon",

year = "2009",

month = nov,

day = "1",

doi = "10.1016/j.jlp.2009.06.013",

language = "English",

volume = "22",

pages = "975--980",

journal = "Journal of Loss Prevention in the Process Industries",

issn = "0950-4230",

publisher = "Elsevier BV",

number = "6",

}

TY - JOUR

T1 - Automatic verification of control logics in safety instrumented system design for chemical process industry

AU - Kim, Jinkyung

AU - Moon, Il

PY - 2009/11/1

Y1 - 2009/11/1

N2 - Automatic model checking is used to determine the error-free design of the SIS (Safety Instrumented System) and to find the logical errors in the chemical processes. It proposes an automatic technique to provide and to modify the P&ID design of SIS control logics. This method can be applied to verify its correctness of SIS and to find the logical errors by synthesizing a feasible sequence automatically. This study focuses on automatic verifying and synthesizing for the design, operability and reachability of SIS control logics in chemical processes.

AB - Automatic model checking is used to determine the error-free design of the SIS (Safety Instrumented System) and to find the logical errors in the chemical processes. It proposes an automatic technique to provide and to modify the P&ID design of SIS control logics. This method can be applied to verify its correctness of SIS and to find the logical errors by synthesizing a feasible sequence automatically. This study focuses on automatic verifying and synthesizing for the design, operability and reachability of SIS control logics in chemical processes.

UR - http://www.scopus.com/inward/record.url?scp=71649097954&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=71649097954&partnerID=8YFLogxK

U2 - 10.1016/j.jlp.2009.06.013

DO - 10.1016/j.jlp.2009.06.013

M3 - Article

AN - SCOPUS:71649097954

VL - 22

SP - 975

EP - 980

JO - Journal of Loss Prevention in the Process Industries

JF - Journal of Loss Prevention in the Process Industries

SN - 0950-4230

IS - 6

ER -