Automatic VHDL model generation system

Sungho Kang, Stephen A. Szygenda

Research output: Chapter in Book/Report/Conference proceedingChapter

1 Citation (Scopus)

Abstract

This paper presents an automatic program synthesis system which generates VHDL models for digital simulators. Behavioral and structural models can be generated from Boolean equations, truth tables, HDL descriptions or schematic diagrams. This system provides an efficient method for automatic model development, which is one of the most difficult task, in a simulation environment.

Original languageEnglish
Title of host publicationIFIP Transactions A
Subtitle of host publicationComputer Science and Technology
PublisherPubl by Elsevier Science Publishers B.V.
Pages353-360
Number of pages8
EditionA-32
ISBN (Print)0444816410
Publication statusPublished - 1993 Dec 1
EventProceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL'93 - Ottawa, Ont, Can
Duration: 1993 Apr 261993 Apr 28

Other

OtherProceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL'93
CityOttawa, Ont, Can
Period93/4/2693/4/28

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Kang, S., & Szygenda, S. A. (1993). Automatic VHDL model generation system. In IFIP Transactions A: Computer Science and Technology (A-32 ed., pp. 353-360). Publ by Elsevier Science Publishers B.V..