Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 2007 Dec 1|
|Event||2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan|
Duration: 2007 Jun 12 → 2007 Jun 14
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering