Band-engineered low PMOS vT with high-K/metal gates featured in a dual channel CMOS integration scheme

H. Rusty Harris, Pankaj Kalra, Prashant Majhi, Muhammed Hussain, David Kelly, Jungwoo Oh, Dawei He, Casey Smith, Joel Barnett, Paul D. Kirsch, Gabriel Gebara, Jess Jur, Daniel Lichtenwalner, Abigail Lubow, T. P. Ma, Guangyu Sung, Scott Thompson, Byoung Hun Lee, Hsing Huang Tseng, Raj Jammy

Research output: Contribution to journalConference articlepeer-review

48 Citations (Scopus)


Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.

Original languageEnglish
Article number4339763
Pages (from-to)154-155
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 2007
Event2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
Duration: 2007 Jun 122007 Jun 14

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


Dive into the research topics of 'Band-engineered low PMOS v<sub>T</sub> with high-K/metal gates featured in a dual channel CMOS integration scheme'. Together they form a unique fingerprint.

Cite this