TY - JOUR
T1 - Band-engineered low PMOS vT with high-K/metal gates featured in a dual channel CMOS integration scheme
AU - Harris, H. Rusty
AU - Kalra, Pankaj
AU - Majhi, Prashant
AU - Hussain, Muhammed
AU - Kelly, David
AU - Oh, Jungwoo
AU - He, Dawei
AU - Smith, Casey
AU - Barnett, Joel
AU - Kirsch, Paul D.
AU - Gebara, Gabriel
AU - Jur, Jess
AU - Lichtenwalner, Daniel
AU - Lubow, Abigail
AU - Ma, T. P.
AU - Sung, Guangyu
AU - Thompson, Scott
AU - Lee, Byoung Hun
AU - Tseng, Hsing Huang
AU - Jammy, Raj
N1 - Copyright:
Copyright 2011 Elsevier B.V., All rights reserved.
PY - 2007
Y1 - 2007
N2 - Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.
AB - Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.
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U2 - 10.1109/VLSIT.2007.4339763
DO - 10.1109/VLSIT.2007.4339763
M3 - Conference article
AN - SCOPUS:37549063505
SP - 154
EP - 155
JO - Digest of Technical Papers - Symposium on VLSI Technology
JF - Digest of Technical Papers - Symposium on VLSI Technology
SN - 0743-1562
M1 - 4339763
T2 - 2007 Symposium on VLSI Technology, VLSIT 2007
Y2 - 12 June 2007 through 14 June 2007
ER -