Abstract
We present a silicon avalanche photodetector (APD) based on multiple P+/N-well junctions fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology. In order to overcome the photodetection-bandwidth limitation of the CMOS-APD based on P+/N-well junction, carrier-acceleration technique is proposed. With this technique, the photogenerated carriers in the charge-neutral N-well region are accelerated by the extrinsic electric field. To induce the extrinsic electric field inside N-well, the CMOS-APD is designed with multiple junctions to reduce the distance between two different N-well biasing contacts. Its performance is simulated and measured with different bias voltages applied to N-well, and it is demonstrated that the CMOS-APD with the carrier-acceleration technique provides higher photodetection bandwidth.
| Original language | English |
|---|---|
| Article number | 7083731 |
| Pages (from-to) | 1387-1390 |
| Number of pages | 4 |
| Journal | IEEE Photonics Technology Letters |
| Volume | 27 |
| Issue number | 13 |
| DOIs | |
| Publication status | Published - 2015 Jul 1 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Electrical and Electronic Engineering
Cite this
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Bandwidth improvement of CMOS-APD with carrier-acceleration technique. / Lee, Myung Jae; Lee, Jeong Min; Rücker, Holger; Choi, Woo Young.
In: IEEE Photonics Technology Letters, Vol. 27, No. 13, 7083731, 01.07.2015, p. 1387-1390.Research output: Contribution to journal › Article
TY - JOUR
T1 - Bandwidth improvement of CMOS-APD with carrier-acceleration technique
AU - Lee, Myung Jae
AU - Lee, Jeong Min
AU - Rücker, Holger
AU - Choi, Woo Young
PY - 2015/7/1
Y1 - 2015/7/1
N2 - We present a silicon avalanche photodetector (APD) based on multiple P+/N-well junctions fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology. In order to overcome the photodetection-bandwidth limitation of the CMOS-APD based on P+/N-well junction, carrier-acceleration technique is proposed. With this technique, the photogenerated carriers in the charge-neutral N-well region are accelerated by the extrinsic electric field. To induce the extrinsic electric field inside N-well, the CMOS-APD is designed with multiple junctions to reduce the distance between two different N-well biasing contacts. Its performance is simulated and measured with different bias voltages applied to N-well, and it is demonstrated that the CMOS-APD with the carrier-acceleration technique provides higher photodetection bandwidth.
AB - We present a silicon avalanche photodetector (APD) based on multiple P+/N-well junctions fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology. In order to overcome the photodetection-bandwidth limitation of the CMOS-APD based on P+/N-well junction, carrier-acceleration technique is proposed. With this technique, the photogenerated carriers in the charge-neutral N-well region are accelerated by the extrinsic electric field. To induce the extrinsic electric field inside N-well, the CMOS-APD is designed with multiple junctions to reduce the distance between two different N-well biasing contacts. Its performance is simulated and measured with different bias voltages applied to N-well, and it is demonstrated that the CMOS-APD with the carrier-acceleration technique provides higher photodetection bandwidth.
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U2 - 10.1109/LPT.2015.2421811
DO - 10.1109/LPT.2015.2421811
M3 - Article
AN - SCOPUS:84933502708
VL - 27
SP - 1387
EP - 1390
JO - IEEE Photonics Technology Letters
JF - IEEE Photonics Technology Letters
SN - 1041-1135
IS - 13
M1 - 7083731
ER -