BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability

Nohjung Kwak, Sang Tae Ahn, Hyung Soon Park, Seo Min Kim, Jin Ki Jung, Gyu Hyun Kim, Geun Young Choi, Dong Chul Koo, Tae Oh Jung, Ja Chun Ku, Jae Kwan Jung, Jinwoong Kim, Sungwook Park, Hyunchul Sohn, Soo Hyun Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (M1 single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers
PublisherIEEE Computer Society
Pages150-152
Number of pages3
ISBN (Print)1424410703, 9781424410705
DOIs
Publication statusPublished - 2007 Jan 1
EventIEEE 2007 International Interconnect Technology Conference, IITC - Burlingame, CA, United States
Duration: 2007 Jun 42007 Jun 6

Publication series

NameProceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Other

OtherIEEE 2007 International Interconnect Technology Conference, IITC
CountryUnited States
CityBurlingame, CA
Period07/6/407/6/6

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics

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    Kwak, N., Ahn, S. T., Park, H. S., Kim, S. M., Jung, J. K., Kim, G. H., Choi, G. Y., Koo, D. C., Jung, T. O., Ku, J. C., Jung, J. K., Kim, J., Park, S., Sohn, H., & Kim, S. H. (2007). BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability. In Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers (pp. 150-152). [4263679] (Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers). IEEE Computer Society. https://doi.org/10.1109/iitc.2007.382367