We describe a prototype multi-partition aware new memory controller and subsystem, BIBIM, which precisely integrates DRAM with 3x nm phase change RAM (PRAM) modules. In this work, we reveal the main challenges of a new type of PRAMs in getting closer to a main processor by evaluating our real 3x nm PRAM with diverse persistent memory benchmarks. BIBIM implements hybrid cache logic into a 2x nm FPGA device, which can hide the long latency imposed by the underlying PRAM modules as well as can support persistent operations. The cache logic of our controller is also able to serve multiple read requests while writing data into a target PRAM bank by considering the multi-partition architecture of such new memory. The evaluation results demonstrate that the read and write latencies of our BIBIM are 115 ns and 125 ns, which are 38% and 99% shorter than those of a pure PRAM-based memory subsystem. In addition, BIBIM can remove blocking reads by 53%, on average, thereby shortening the average latency of write-after-read memory operations by 48%.
|Publication status||Published - 2018|
|Event||10th USENIX Workshop on Hot Topics in Storage and File Systems, HotStorage 2018, co-located with USENIX ATC 2018 - Boston, United States|
Duration: 2018 Jul 9 → 2018 Jul 10
|Conference||10th USENIX Workshop on Hot Topics in Storage and File Systems, HotStorage 2018, co-located with USENIX ATC 2018|
|Period||18/7/9 → 18/7/10|
Bibliographical noteFunding Information:
This work is supported by MemRay grant (2015-11-1731). The authors thank Swapnil Haria and Pratyush Mahapatra who prepared the trace collection environment. Gyuyoung Park and Miryeong Kwon equally contribute to this work. The authors also thank MemRay and Samsung for their engineering sample donations and technical support. Myoungsoo Jung is the corresponding author.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Information Systems
- Computer Networks and Communications