As manufacturing process technology scales down, memory capacity and density continue to grow. As the number of memory cells per area increases, so does the possibility of having defects in the memory cells. Therefore, built-in redundancy analysis (BIRA) is widely used for memory test and repair. BIRA repairs faulty cells by replacing them with healthy spare cells. To perform BIRA, the faulty memory cell information is required and is collected via a memory test. By using the faulty cell information, BIRA can analyze and perform the repair by assigning spares to defective cells. However, it requires extra hardware to store the faulty cell information. Most conventional BIRA approaches utilize content-addressable memories (CAMs) to store faulty cell information. Owing to the CAMs' fast access speed, the repair time can be reduced. However, CAMs are the critical source of an area overhead for BIRA, and a CAM could be shared across multiple memory banks. The shared structure limits simultaneous repair operations for the banks, and when the CAM is faulty, the conventional CAM-based BIRA cannot be performed. This paper proposes a new BIRA method, which does not require extra memory and instead utilizes a fault-free memory region to store the faulty cell information. Because extra memory is not required in the proposed BIRA method, the area overhead is decreased. The proposed hierarchical repair algorithm thus helps to reduce the analysis time, while achieving optimal normalized repair rate.
|Number of pages||12|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - 2017 Dec|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering