A bit-line sense amplifier using PMOS charge transfer pre-sensing (CTPS) circuit is proposed. The CTPS circuit using charge sharing operation between lines which have different capacitance is useful for increasing small bit-line voltage differences. The PMOS latch transistors of CTPS circuit are used for pre-sensing operation and pull-up latching operation. Because the PMOS latch transistors are used mutually, area overhead of the CTPS is minimized. The PMOS CTPS circuit increases the small bit-line voltage difference and the output voltage difference of the CTPS circuit becomes the input voltage difference of the latch sense amplifier. Using the PMOS CTPS circuit, the speed of read operation and the reliability of the read operation is improved. The performance of the proposed scheme is verified by the simulation using a 45 nm process.
|Title of host publication||Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||5|
|Publication status||Published - 2019 Feb 22|
|Event||2018 IEEE Region 10 Conference, TENCON 2018 - Jeju, Korea, Republic of|
Duration: 2018 Oct 28 → 2018 Oct 31
|Name||IEEE Region 10 Annual International Conference, Proceedings/TENCON|
|Conference||2018 IEEE Region 10 Conference, TENCON 2018|
|Country||Korea, Republic of|
|Period||18/10/28 → 18/10/31|
Bibliographical noteFunding Information:
The EDA tool was supported by the IC Design Education Center (IDEC), Korea.
ACKNOWLEDGMENT This research was supported by the MOTIE (Ministry of Trade, Industry & Energy) (10080722) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering